MEMORY DEVICE STORING SETTING DATA AND OPERATING METHOD THEREOF

    公开(公告)号:US20230042249A1

    公开(公告)日:2023-02-09

    申请号:US17722850

    申请日:2022-04-18

    Abstract: Provided are a memory device storing setting data and a memory system including the same. The memory device may include a cell array including a plurality of cell blocks, each including a plurality of pages, and a control logic that controls a program and read operation on the cell array, wherein at least one page of the cell array stores information data read (IDR) data including information related to a setting operation of the memory device, at least one other page of the cell array stores replica IDR data including inverted bit values of the IDR data, and the control logic controls a recovery operation for repairing errors in the IDR data by reading the replica IDR data when a read fail of the IDR data occurs.

    NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING NONVOLATILE MEMORY DEVICE

    公开(公告)号:US20230143210A1

    公开(公告)日:2023-05-11

    申请号:US17750315

    申请日:2022-05-21

    CPC classification number: G11C16/26 G11C16/0483 G11C16/08 G11C16/24

    Abstract: In a method of operating a nonvolatile memory device that includes a memory block including cell strings where each of the cell strings includes a string selection transistor, memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction, each of word-lines coupled to the memory cells is set up to a respective target level during a word-line set-up period, a sensing operation on target memory cells is performed by applying a read voltage to a selected word-line coupled to the target memory cells while applying a read pass voltage to unselected word-lines during a sensing period, and while consuming an internal voltage connected to the unselected word-lines in a particular circuit in the nonvolatile memory device, a voltage level of the unselected word-lines is recovered to a level of the internal voltage during a discharge period of a word-line recovery period.

    NON-VOLATILE MEMORY DEVICE
    4.
    发明申请

    公开(公告)号:US20230116928A1

    公开(公告)日:2023-04-20

    申请号:US17742874

    申请日:2022-05-12

    Abstract: A non-volatile memory device includes a plurality of word lines stacked above a substrate in a vertical direction; erase control lines that are spaced apart from each other in a first direction and extend in a second direction; a pass transistor circuit including a first pass transistor connected to a first group of erase control lines and a second pass transistor connected to a second group of erase control lines; and a memory cell array including a plurality of blocks. The first group of erase control lines are relatively close to a word line cut region and the second group of erase control lines are relatively far from the word line cut region. Each of the plurality of blocks includes a plurality of channel structures connected to the word lines and the erase control lines and each channel structure extends in the vertical direction.

    NONVOLATILE MEMORY DEVICE
    5.
    发明申请

    公开(公告)号:US20220075565A1

    公开(公告)日:2022-03-10

    申请号:US17455037

    申请日:2021-11-16

    Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

    METHOD AND APPARATUS FOR FEEDBACK IN MOBILE COMMUNICATION SYSTEM
    6.
    发明申请
    METHOD AND APPARATUS FOR FEEDBACK IN MOBILE COMMUNICATION SYSTEM 审中-公开
    移动通信系统中反馈的方法和装置

    公开(公告)号:US20160338052A1

    公开(公告)日:2016-11-17

    申请号:US15153132

    申请日:2016-05-12

    CPC classification number: H04L5/0055 H04L1/12 H04L5/1469 H04W72/1289

    Abstract: A method and apparatus for feedback in a mobile communication system are provided. The method of feedback transmission for a user equipment (UE) in a wireless communication system includes receiving control information indicating whether a subframe of an uplink band is allocated for a downlink from a base station (BS), receiving data from the BS in at least three subframes according to the control information, and sending the BS feedback for the data received in the at least three subframes using transmission time interval (TTI) bundling.

    Abstract translation: 提供了一种用于移动通信系统中的反馈的方法和装置。 用于无线通信系统中的用户设备(UE)的反馈传输方法包括接收控制信息,该控制信息指示是否从基站(BS)为下行链路分配了上行链路频带的子帧,至少从BS接收数据 根据所述控制信息的三个子帧,以及使用传输时间间隔(TTI)捆绑在所述至少三个子帧中接收的数据发送所述BS反馈。

    NON-VOLATILE MEMORY DEVICE
    8.
    发明申请

    公开(公告)号:US20230138604A1

    公开(公告)日:2023-05-04

    申请号:US17748156

    申请日:2022-05-19

    Abstract: Provided is a non-volatile memory device including a memory cell array including cell strings each including memory cells and a string select transistor connected to a string select line; a page buffer circuit including page buffers each including a forcing latch configured to store forcing information; and a control logic circuit configured to, during a program operation on a selected word line, control at least two of a first voltage applied to the string select line in a first interval before a bit line forcing operation for transferring the forcing information to the selected cell string, a second voltage applied to the string select line in a second interval in which the bit line forcing operation is performed, and a third voltage applied to the string select line in a third interval after the bit line forcing operation is performed, to be different from each other.

    NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING INITIALIZATION OF THE SAME

    公开(公告)号:US20210034295A1

    公开(公告)日:2021-02-04

    申请号:US16807405

    申请日:2020-03-03

    Abstract: A method includes performing a first sensing operation to sense write setting data stored in first memory cells of a first memory plane and store first read setting data in a first page buffer circuit of the first memory plane, performing a second sensing operation to sense the write setting data stored in second memory cells of a second memory plane and store second read setting data in a second page buffer circuit of the second memory plane and performing a dump-down operation to store restored setting data corresponding to the write setting data in a buffer based on the first read setting data and the second read setting data.

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