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    Semiconductor device including multi-stack structure
    11.
    发明授权
    Semiconductor device including multi-stack structure 有权

    公开(公告)号：US11882701B2

    公开(公告)日：2024-01-23

    申请号：US17333407

    申请日：2021-05-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Cheon Baek

    IPC: H10B43/27 ,  H01L29/66 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50

    CPC classification number: H10B43/27 ,  H01L29/66833 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50

    Abstract: A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers.

    Three-dimensional semiconductor device
    12.
    发明授权
    Three-dimensional semiconductor device 有权

    公开(公告)号：US11476265B2

    公开(公告)日：2022-10-18

    申请号：US16401205

    申请日：2019-05-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Cheon Baek

    IPC: H01L27/11556 ,  H01L27/02 ,  G11C5/06 ,  H01L27/11582

    Abstract: A three-dimensional semiconductor device comprises a stack structure on a lower structure, a vertical channel structure passing through the stack structure, and a first vertical support structure passing through the stack structure and spaced apart from the vertical channel structure. The stack structure includes interlayer insulation layers and gate horizontal patterns, alternately stacked in a vertical direction perpendicular to an upper surface of the lower structure. The vertical channel structure and the first vertical support structure have different cross-sectional shapes. The vertical channel structure further includes a channel semiconductor layer. The vertical channel structure includes first and second vertical regions, and a width variation portion between the first and second vertical regions. The interlayer insulation layers include an intermediate interlayer insulation layer adjacent to the width variation portion. The intermediate interlayer insulation layer has the same thickness as that of an interlayer insulation layer adjacent in the vertical direction.

    SEMICONDUCTOR DEVICES INCLUDING CHANNEL STRUCTURES
    13.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING CHANNEL STRUCTURES 审中-公开

    公开(公告)号：US20200185402A1

    公开(公告)日：2020-06-11

    申请号：US16454293

    申请日：2019-06-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： YOON HWAN SON ,  Seok Cheon Baek ,  Ji Sung Cheon

    IPC: H01L27/11578 ,  H01L27/11565 ,  H01L27/11568

    Abstract: A semiconductor device may include a substrate and a stacked structure in which a plurality of insulating layers and a plurality of interconnection layers are alternately stacked on the substrate. An isolation region may cross the stacked structure in a first direction. A plurality of first structures may extend into the stacked structure in a second direction perpendicular to the first direction. A plurality of first patterns may extend into the stacked structure in the second direction in the isolation region. Bottoms of the plurality of first patterns may be farther from an upper surface of the substrate than bottoms of the plurality of channel structures.

    Vertical memory device
    17.
    发明授权
    Vertical memory device 有权

    公开(公告)号：US11264401B2

    公开(公告)日：2022-03-01

    申请号：US16270570

    申请日：2019-02-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun Hyoung Kim ,  Kwang Soo Kim ,  Seok Cheon Baek ,  Geun Won Lim

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157

    Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

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