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公开(公告)号:US11188704B2
公开(公告)日:2021-11-30
申请号:US16915369
申请日:2020-06-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jin-Tae Kim , Jung-Ho Do , Tae-Joong Song , Doo-Hee Cho , Seung-Young Lee
IPC: G06F30/33 , G06F30/394 , G06F30/392
Abstract: A method of designing an integrated circuit includes receiving input data defining the integrated circuit, receiving information from a standard cell library including a plurality of standard cells, receiving information from a modified cell library including at least one modified cell having a same function as a corresponding standard cell among the plurality of standard cells and having a higher routability than the corresponding standard cell and generating output data by performing placement and routing in response to the input data, the information from the standard cell library and the information from the modified cell library.
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公开(公告)号:US10990740B2
公开(公告)日:2021-04-27
申请号:US16378751
申请日:2019-04-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jin-Tae Kim , Sung-We Cho , Tae-Joong Song , Seung-Young Lee , Jin-Young Lim
IPC: G06F30/392 , H01L27/02 , G06F30/394 , G06F30/398
Abstract: An integrated circuit may include a first standard cell including first and second active regions extending in a first horizontal direction and a first gate line extending in a second horizontal direction orthogonal to the first horizontal direction; and a second standard cell including third and fourth active regions extending in the first horizontal direction and a second gate line aligned in parallel to the first gate in the second horizontal direction and being adjacent to the first standard cell. A distance between the second active region of the first standard cell and the third active region of the second standard cell may be greater than a distance between the first and second active regions of the first standard cell, and may be greater than a distance between the third and fourth active regions of the second standard cell.
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公开(公告)号:US20200034508A1
公开(公告)日:2020-01-30
申请号:US16589360
申请日:2019-10-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jung-Ho Do , Jong-Hoon Jung , Seung-Young Lee , Tae-Joong Song
Abstract: An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.
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公开(公告)号:US20190355750A1
公开(公告)日:2019-11-21
申请号:US16409129
申请日:2019-05-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-ho Do , Ji-Su Yu , Hyeon-gyu You , Seung-Young Lee , Jae-Boong Lee , Jong-Hoon Jung
IPC: H01L27/118 , H01L27/02
Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.
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公开(公告)号:US20180294226A1
公开(公告)日:2018-10-11
申请号:US15946075
申请日:2018-04-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jae-Boong Lee , Jung-Ho Do , Tae-Joong Song , Seung-Young Lee , Jong-Hoon Jung , Ji-Su Yu
IPC: H01L23/528 , H01L27/02 , H01L23/522 , H01L21/8234
Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.
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公开(公告)号:US11289469B2
公开(公告)日:2022-03-29
申请号:US17038292
申请日:2020-09-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seung-Young Lee , Jong-hoon Jung , Myoung-ho Kang , Jung-ho Do
IPC: H01L27/02 , G11C11/419 , G11C11/40 , H01L23/528 , H01L27/105 , H01L27/118 , G11C5/14 , G11C7/18
Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.
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公开(公告)号:US11201150B2
公开(公告)日:2021-12-14
申请号:US16746071
申请日:2020-01-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sang-Hoon Baek , Sun-Young Park , Sang-Kyu Oh , Ha-young Kim , Jung-Ho Do , Moo-Gyu Bae , Seung-Young Lee
IPC: H01L23/48 , H01L29/40 , H01L27/088 , H01L27/02 , H01L27/11 , H01L21/84 , H01L27/12 , H01L21/8234 , H01L23/528
Abstract: A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact.
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公开(公告)号:US10811357B2
公开(公告)日:2020-10-20
申请号:US15946075
申请日:2018-04-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jae-Boong Lee , Jung-Ho Do , Tae-Joong Song , Seung-Young Lee , Jong-Hoon Jung , Ji-Su Yu
IPC: H01L23/528 , H01L27/02 , H01L23/522 , H01L21/8234 , H01L27/118 , G06F30/327 , G06F30/394 , H01L27/088 , H01L27/092 , G06F30/392
Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.
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公开(公告)号:US10445455B2
公开(公告)日:2019-10-15
申请号:US15689008
申请日:2017-08-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jung-Ho Do , Jong-Hoon Jung , Seung-Young Lee , Tae-Joong Song
Abstract: An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.
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公开(公告)号:US20180096092A1
公开(公告)日:2018-04-05
申请号:US15585548
申请日:2017-05-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: JIN-TAE KIM , Jung-Ho Do , Tae-Joong Song , Doo-Hee Cho , Seung-Young Lee
IPC: G06F17/50
Abstract: A method of designing an integrated circuit includes receiving input data defining the integrated circuit, receiving information from a standard cell library including a plurality of standard cells, receiving information from a modified cell library including at least one modified cell having a same function as a corresponding standard cell among the plurality of standard cells and having a higher routability than the corresponding standard cell and generating output data by performing placement and routing in response to the input data, the information from the standard cell library and the information from the modified cell library.
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