公开(公告)号：US11056158B2

公开(公告)日：2021-07-06

申请号：US16571868

申请日：2019-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Seok Kang ,  Seungjun Bae

IPC: G11C7/10 ,  G06F3/06 ,  H03L7/091 ,  H03L7/081 ,  G11C29/02 ,  H03L7/08 ,  H04L7/10 ,  H04L7/033 ,  G11C7/22 ,  H03L7/085 ,  H04L7/00 ,  H04L7/08 ,  H04L25/02

Abstract: A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.

公开(公告)号：US10969420B2

公开(公告)日：2021-04-06

申请号：US16023736

申请日：2018-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Jung Kwon ,  Seungjun Bae

IPC: G01R31/02 ,  G01R31/26 ,  H03K3/03 ,  G01R31/317 ,  G01R31/28 ,  H01L21/66

Abstract: A test circuit includes a first logic gate that receives a test signal or a first voltage, a second logic gate that receives the test signal, a third logic gate that receives an output of the first logic gate, an output of the second logic gate, or a second voltage, a fourth logic gate that receives the output of the first logic gate or the output of the second logic gate, and a power circuit that prevents the second and fourth logic gates from being driven by supplying power to the second and fourth logic gates when the first logic gate receives the first voltage and the third logic gate receives the second voltage.

公开(公告)号：US20200168259A1

公开(公告)日：2020-05-28

申请号：US16778431

申请日：2020-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C8/18 ,  G06F11/10 ,  G11C11/4076 ,  G11C7/22 ,  G11C5/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：US10593387B2

公开(公告)日：2020-03-17

申请号：US16274860

申请日：2019-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C8/00 ,  G11C8/18 ,  G11C5/04 ,  G11C7/22 ,  G11C11/4076 ,  G06F11/10 ,  G11C29/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：US10453504B2

公开(公告)日：2019-10-22

申请号：US15689260

申请日：2017-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Seok Kang ,  Seungjun Bae

IPC: G11C7/10 ,  G11C7/22 ,  H03L7/085 ,  H04L7/00 ,  H04L7/08 ,  H04L25/02 ,  G11C29/02 ,  H03L7/08 ,  H03L7/081 ,  H03L7/091 ,  H04L7/033 ,  H04L7/10

Abstract: A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.