公开(公告)号：US09306583B2

公开(公告)日：2016-04-05

申请号：US14638363

申请日：2015-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soon Suk Hwang ,  Youngjin Cho ,  Kyuwook Han ,  Jaegeun Park

IPC: G11C7/00 ,  H03L7/08 ,  H03L7/085 ,  G11C7/22

CPC classification number: H03L7/0802 ,  G06F1/04 ,  G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/085 ,  H03L2207/50 ,  Y02D10/14

Abstract: A delay locked loop (DLL) is provided. The DLL includes a delay line, a phase detector, a delay line control unit, and a DLL controller. The delay line outputs an output clock by delaying an input clock by a first time on the basis of a select value. The phase detector detects a phase of the output clock. The delay line control unit determines a select value so that the first time corresponds to n periods of the input clock on the basis of the detected phase and an initial select value. The DLL controller provides the initial select value to the delay line control unit. The DLL controller updates the initial select value according to a change of a frequency of the input clock, and to provide the updated initial select value to the delay line control unit.

Abstract translation: 提供延迟锁定环（DLL）。 DLL包括延迟线，相位检测器，延迟线控制单元和DLL控制器。 延迟线通过基于选择值第一次延迟输入时钟来输出输出时钟。 相位检测器检测输出时钟的相位。 延迟线控制单元确定选择值，使得第一时间基于检测到的相位和初始选择值对应于输入时钟的n个周期。 DLL控制器向延迟线控制单元提供初始选择值。 DLL控制器根据输入时钟频率的变化来更新初始选择值，并向延迟线控制单元提供更新的初始选择值。

公开(公告)号：US11836041B2

公开(公告)日：2023-12-05

申请号：US17900336

申请日：2022-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulseung Lee ,  Soon Suk Hwang ,  Choongeui Lee

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C7/10 ,  G11C7/22

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/1084 ,  G11C7/22 ,  G11C29/52 ,  G11C2207/2254

Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.

公开(公告)号：US11137921B2

公开(公告)日：2021-10-05

申请号：US16560417

申请日：2019-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Jin Cho ,  Hyo Deok Shin ,  Kyung Bo Yang ,  Youn Ho Jeon ,  Hyeok Jun Choe ,  Jung Hyun Hong ,  Soon Suk Hwang

IPC: G06F3/06

Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.

公开(公告)号：US10970164B2

公开(公告)日：2021-04-06

申请号：US16248540

申请日：2019-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulseung Lee ,  Soon Suk Hwang ,  Choongeui Lee

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C7/10 ,  G11C7/22

Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.

公开(公告)号：US20200285392A1

公开(公告)日：2020-09-10

申请号：US16560417

申请日：2019-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Jin CHO ,  Hyo Deok Shin ,  Kyung Bo Yang ,  Youn Ho Jeon ,  Hyeok Jun Choe ,  Jung Hyun Hong ,  Soon Suk Hwang

IPC: G06F3/06

Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.

公开(公告)号：US10564876B2

公开(公告)日：2020-02-18

申请号：US15804226

申请日：2017-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghoon Woo ,  Soon Suk Hwang

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/10 ,  G06F13/28 ,  G11C29/52

Abstract: A storage device includes nonvolatile memory devices arranged in groups, and a controller connected with the groups respectively through channels. The controller is configured to generate an access request for a nonvolatile memory device among the nonvolatile memory devices, and transmit, based on the access request, access requests respectively to two or more groups, among the groups, respectively through two or more channels, among the channels.

公开(公告)号：US10509575B2

公开(公告)日：2019-12-17

申请号：US15404229

申请日：2017-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonghoon Woo ,  Haksun Kim ,  Taemin Jeong ,  Kyuwook Han ,  Soon Suk Hwang

IPC: G06F3/06 ,  G06F12/14 ,  G06F9/4401

Abstract: A storage device includes a nonvolatile memory device, and a controller configured to control the nonvolatile memory device based on metadata. The controller encrypts the metadata and loads the encrypted metadata on a random access memory of an external host device.