公开(公告)号：US20220358345A1

公开(公告)日：2022-11-10

申请号：US17591114

申请日：2022-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo KIM ,  Sungmeen MYUNG

IPC: G06N3/04

Abstract: A computing device for a multidimensional vector neural network includes: input lines to which multidimensional input vectors are input; output lines intersecting the input lines; memory cells disposed at intersecting points between the input lines and the output lines and configured to store weight elements included in multidimensional weight vectors; selectors configured to transmit a value output from each of the output lines to any one of adders; and the adders configured to accumulate values received from the selectors in a predetermined number of cycles, wherein, for each of the multidimensional weight vectors, weight elements included in the multidimensional weight vector are stored in reference memory cells that connect a corresponding single reference input line and corresponding two or more reference output lines.

公开(公告)号：US20220019884A1

公开(公告)日：2022-01-20

申请号：US17194571

申请日：2021-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchul JUNG ,  Sangjoon KIM ,  Sungmeen MYUNG

IPC: G06N3/063 ,  G11C11/4094

Abstract: A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.

公开(公告)号：US20240086153A1

公开(公告)日：2024-03-14

申请号：US18467521

申请日：2023-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmeen MYUNG ,  Dong-Jin CHANG ,  Jaehyuk LEE ,  Daekun YOON ,  Seok Ju YUN

IPC: G06F7/544 ,  G06F7/40

CPC classification number: G06F7/5443 ,  G06F7/405

Abstract: A multi-bit accumulator includes 1-bit Wallace trees each configured to perform an add operation on single-bit input data, tristate logic circuits each configured to output a result of the add operation of the 1-bit Wallace trees according to an enable signal provided to the tristate logic circuits, and a shift-adder configured to perform an accumulation operation on the result of the add operation of the 1-bit Wallace trees by a shift operation based on a clock signal.

公开(公告)号：US20240071548A1

公开(公告)日：2024-02-29

申请号：US18091258

申请日：2022-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmeen MYUNG ,  Seok Ju YUN ,  Jaehyuk LEE ,  Seungchul JUNG

IPC: G11C29/36 ,  G11C29/00 ,  G11C29/44

CPC classification number: G11C29/36 ,  G11C29/44 ,  G11C29/785 ,  G11C2029/3602

Abstract: A method and memory device with in-memory computing defection detection is disclosed. A memory device includes a memory including banks, wherein each bank includes a respective plurality of bit-cells, an in-memory computation (IMC) operator configured to perform an IMC operation between first data while the first data is in the bit-cells of the memory and second data received as input to the memory device, wherein the banks share the operator, and wherein the memory device is configured to: generate a first test pattern that is stored in the memory and generate a second test pattern applied to the IMC operator, and based thereon determine whether a defect has occurred in either the memory or the operator, and perform a repair based on the determination that a defect has occurred.

公开(公告)号：US20230155578A1

公开(公告)日：2023-05-18

申请号：US17702170

申请日：2022-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchul JUNG ,  Sang Joon KIM ,  Sungmeen MYUNG ,  Seok Ju YUN ,  Seungkeun YOON

IPC: H03K3/037 ,  H03K21/08

CPC classification number: H03K3/037 ,  H03K21/08

Abstract: A computing device for performing a digital pulse-based crossbar operation and a method of operating the computing device. The computing device includes a plurality of input lines to which a pulse is selectively input in a sequential manner based on a corresponding input signal; a plurality of output lines crossing the input lines; a plurality of elements, each element being disposed at a cross point between a corresponding input line and a corresponding output line to transfer, to the corresponding output line, a pulse input to the corresponding input line in response to a corresponding weight being a first value; and a plurality of pulse counters, each pulse counter counting a number of pulses output from a corresponding output line.

公开(公告)号：US20230075348A1

公开(公告)日：2023-03-09

申请号：US17735492

申请日：2022-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyuk LEE ,  Sang Joon KIM ,  Seungchul JUNG ,  Sungmeen MYUNG

IPC: G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  H03K19/21 ,  G06N3/04

Abstract: A multiplier-accumulator includes: a plurality of exclusive negative OR (XNOR) gates provided along one or more input lines and configured to receive signals corresponding to an input bit sequence and a weight bit sequence corresponding to each of the one or more input lines and to output partial product results between the input bit sequence and the weight bit sequence; an encoder configured to apply, to the plurality of XNOR gates, a signal corresponding to a sequence in which a logical value of a most significant bit (MSB) is converted from an original sequence expressed in 2's complement of a corresponding sequence for either one or both of the input bit sequence and the weight bit sequence; and an outputter configured to generate an output in which a correction value is applied to operation results in which the partial product results output from the plurality of XNOR gates are summed.

公开(公告)号：US20220326910A1

公开(公告)日：2022-10-13

申请号：US17473139

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmeen MYUNG ,  Seungchul JUNG ,  Sangjoon KIM

IPC: G06F7/50 ,  G11C11/56 ,  G06F7/523 ,  G06N3/063 ,  G06N3/04

Abstract: A multi-bit cell includes: a memory storing a weight resistance corresponding to a multi-bit weight; a current source configured to apply a current to the memory to generate a weight voltage from the weight resistance; a plurality of multiplexers connected to each other in parallel and connected to the memory in series, each of the multiplexers being configured to output one signal of the weight voltage and a first fixed voltage based on a multi-bit input; and a plurality of capacitors connected to the plurality of multiplexers, respectively, each of the capacitors being configured to store a respective weight capacitance, and to generate charge data by performing an operation on the outputted signal and the weight capacitance.

公开(公告)号：US20220114427A1

公开(公告)日：2022-04-14

申请号：US17238403

申请日：2021-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchul JUNG ,  Hyungwoo LEE ,  Sungmeen MYUNG ,  Yongmin JU

IPC: G06N3/063 ,  G06F7/544

Abstract: A neural network apparatus includes: a plurality of memory cells each comprising a variable resistance element and a first transistor; a plurality of bit lines extending in a first direction; and a plurality of word lines extending in a second direction, crossing the bit lines and respectively connected to the first transistor of the plurality of memory cells; a plurality of sub-column circuits each comprising memory cells of the memory cells connected in parallel along the first direction; and a column circuit comprising two or more of the sub-column circuits connected in series along the second direction, wherein, when a neural network operation is performed, the column circuit outputs a summation current to a bit line connected to the column circuit based on voltage applied to the plurality of word lines.