公开(公告)号：US12009299B2

公开(公告)日：2024-06-11

申请号：US18137733

申请日：2023-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Hyuk Choi ,  Wonchul Lee ,  Joonhyoung Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L29/0649

Abstract: A semiconductor device includes; a semiconductor substrate including a first region and a second region, a first interlayer insulating layer on the second region, a capping layer disposed on the first interlayer insulating layer, an upper surface of the capping layer includes a first trench, conductive patterns spaced apart on the capping layer, side surfaces of the conductive patterns are aligned with inner side surfaces of the first trench, and a peripheral separation pattern disposed in the first trench to cover the side surfaces of the conductive patterns. The peripheral separation pattern has a first thickness on the side surfaces of the conductive patterns and a second thickness greater than or equal to the first thickness on a lower surface.

公开(公告)号：US11329050B2

公开(公告)日：2022-05-10

申请号：US16993394

申请日：2020-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin Seong ,  Dongsoo Woo ,  Wonchul Lee

IPC: H01L27/108

Abstract: A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.

公开(公告)号：US11195837B2

公开(公告)日：2021-12-07

申请号：US16800105

申请日：2020-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hoon Song ,  Kiheum Nam ,  Wonchul Lee

IPC: H01L27/108 ,  H01L49/02 ,  H01L23/528 ,  H01L21/768 ,  H01L29/41 ,  H01L27/02

Abstract: A semiconductor device comprises a plurality of pillars on a semiconductor substrate, and a support pattern in contact with at least one side surface of each of the pillars. The support pattern connects the pillars with one another. The support pattern includes a plurality of support holes that expose side surfaces of the pillars. The support holes includes a first support hole and a second support hole that are spaced apart from each other. The pillars have circular cross-sections. A ribbon-like hexagon is obtained in a plan view when connecting an inner sidewall of the first support hole with central points of the cross-sections of the pillars exposed through the first support hole.

公开(公告)号：US20240282703A1

公开(公告)日：2024-08-22

申请号：US18652628

申请日：2024-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Hyuk Choi ,  Wonchul Lee ,  Joonhyoung Yang

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L29/0649

Abstract: A semiconductor device includes; a semiconductor substrate including a first region and a second region, a first interlayer insulating layer on the second region, a capping layer disposed on the first interlayer insulating layer, an upper surface of the capping layer includes a first trench, conductive patterns spaced apart on the capping layer, side surfaces of the conductive patterns are aligned with inner side surfaces of the first trench, and a peripheral separation pattern disposed in the first trench to cover the side surfaces of the conductive patterns. The peripheral separation pattern has a first thickness on the side surfaces of the conductive patterns and a second thickness greater than or equal to the first thickness on a lower surface.

公开(公告)号：US20240266170A1

公开(公告)日：2024-08-08

申请号：US18500662

申请日：2023-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghwan Lee ,  Kanguk Kim ,  Seokhyun Kim ,  Wonchul Lee

IPC: H01L21/027 ,  H01L21/308 ,  H10B12/00

CPC classification number: H01L21/0276 ,  H01L21/3081 ,  H01L21/3086 ,  H10B12/09

Abstract: A method of forming a pattern includes forming an etch target layer over a substrate including a first area and a second area, forming a hardmask structure over the etch target layer, forming a photoresist pattern including a first photoresist pattern including an engraved pattern located in the first area and a second photoresist pattern including an embossed pattern located in the second area, forming an upper hardmask pattern including a plurality of openings, forming a reversible hardmask pattern filling the plurality of openings in the first area, and forming a feature pattern including a first pattern located in the first area and a second pattern located in the second area, wherein the first pattern includes a plurality of island patterns and a dam structure planarly surrounding the plurality of island patterns.

公开(公告)号：US11968823B2

公开(公告)日：2024-04-23

申请号：US17716194

申请日：2022-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin Seong ,  Dongsoo Woo ,  Wonchul Lee

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485 ,  H10B12/50

Abstract: A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.

公开(公告)号：US20230133763A1

公开(公告)日：2023-05-04

申请号：US17868126

申请日：2022-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunyoung Lee ,  Sohyeon Bae ,  Wonchul Lee

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate having a cell array region, a peripheral circuit region, and a connection region, a device separation region including a first device separation layer defining a cell active region on the cell array region, a second device separation layer defining a peripheral active region on the peripheral circuit region, and a third device separation layer defining an active dam on the connection region, a gate structure including a gate electrode crossing the cell active region on the cell array region, extending into the third device separation layer on the connection region, and having an end surface in the third device separation layer, and a gate contact plug electrically connected to the gate electrode on the connection region, wherein the third device separation layer includes a first insulating liner, a second insulating liner on the first insulating liner, and an embedded insulating layer.

公开(公告)号：US10720435B2

公开(公告)日：2020-07-21

申请号：US16440399

申请日：2019-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hoon Song ,  Kiheum Nam ,  Wonchul Lee

IPC: H01L27/108 ,  H01L29/41 ,  H01L21/768 ,  H01L23/528 ,  H01L49/02 ,  H01L27/02

Abstract: A semiconductor device includes a plurality of pillar structures on a semiconductor substrate, and a support pattern in contact with at least a part of each of the pillar structures, the support pattern connecting the pillar structures with one another, wherein the support pattern includes support holes exposing side surfaces of the pillar structures, the support holes including at least a first support hole and a second support hole that are spaced apart from each other, the first and second support holes having different shapes from each other.

公开(公告)号：US20180342519A1

公开(公告)日：2018-11-29

申请号：US15814824

申请日：2017-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Kim ,  Wonchul Lee

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10852 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10894 ,  H01L28/75 ,  H01L28/87 ,  H01L28/91

Abstract: A semiconductor device includes a substrate including a cell region and peripheral region and bottom electrodes on the substrate. The bottom electrodes are arranged in a first row and a second row each extending in a first direction. The first row and the second row are adjacent to each other in a second direction perpendicular to the first direction. The bottom electrodes in the first row include an outermost bottom electrode and a next outermost bottom electrode that are separated by a first distance in the first direction. The bottom electrodes in the second row include an outermost bottom electrode and a next outermost bottom electrode that are separated by a second distance in the first direction. The outermost bottom electrode in the first row is on the peripheral region of the substrate. The outermost bottom electrode in the second row is on the cell region of the substrate.

公开(公告)号：US09213598B2

公开(公告)日：2015-12-15

申请号：US14175342

申请日：2014-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngil Seo ,  Jungho Yun ,  Wonchul Lee ,  Dawoon Jung

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1048

Abstract: A nonvolatile memory device includes a nonvolatile memory, a buffer memory configured to store a plurality of read data transmitted from the nonvolatile memory, an error detection and correction circuit configured to detect an error in partial data of each of the plurality of read data and judging whether the partial data is correctable or not on the basis of the detected error, and a controller configured to analyze the uncorrectable partial data with respect to the plurality of read data to determine a representative value, and to transmit the representative value to the error detection and correction circuit. The plurality of read data is read through a read operation with respect to a same page.

Abstract translation: 非易失性存储器件包括非易失性存储器，缓冲存储器，被配置为存储从非易失性存储器发送的多个读取数据;错误检测和校正电路，被配置为检测多个读取数据中的每一个的部分数据中的错误，并且判断 基于检测到的错误是否可校正部分数据;以及控制器，被配置为分析关于多个读取数据的不可校正部分数据以确定代表值，并将代表值发送到错误检测 和校正电路。 通过对同一页面的读取操作来读取多个读取数据。