公开(公告)号：US10241922B2

公开(公告)日：2019-03-26

申请号：US15344267

申请日：2016-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woong Seo

IPC: G06F12/00 ,  G06F12/0895 ,  G06F12/0891 ,  G06F12/0888 ,  H04L12/861

Abstract: Provided is a processor including a plurality of devices. The processor includes a source processing device configured to identify data to request from another device, and a destination processing device configured to, in response to a request for the identified data from the source processing device using credit-based flow control, transmit the identified data to the source processing device using the credit-based flow control. The source processing device includes a credit buffer used for the credit-based flow control, the credit buffer being allocable to include a cache region configured to cache the transmitted identified data received by the source processing device.

公开(公告)号：US10019349B2

公开(公告)日：2018-07-10

申请号：US14715683

申请日：2015-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong Hoon Jeong ,  Woong Seo ,  Sang Heon Lee ,  Sun Min Kwon ,  Ho Young Kim ,  Hee Jun Shim

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0846

CPC classification number: G06F12/0207 ,  G06F12/0607 ,  G06F12/0846 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/455

Abstract: A cache memory and a method of managing the same are provided. The method of managing a cache memory includes determining whether a number of bits of a data bandwidth stored in a bank is an integer multiple of a number of bits of unit data in data to be stored, storing first unit data, among the data to be stored, in a first region of a first address in the bank in response to the number of bits of the data bandwidth not being the integer multiple of the number of bits of the unit data, and storing part of second unit data, among the data to be stored, in a second region of the first address.

公开(公告)号：US10257076B2

公开(公告)日：2019-04-09

申请号：US15132663

申请日：2016-04-19

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Sungju Han ,  Jinho Lee ,  Kiyoung Choi ,  Woong Seo

IPC: H04L12/44 ,  H04L12/733 ,  H04L12/741 ,  H04L12/727 ,  H04L12/947 ,  H04L12/54 ,  H04L12/933

Abstract: Provided is a multi network and method to transmit packets. The multi network includes a mesh network, a tree network, and a network interface connected to the mesh network and the tree network and configured to transmit, through the mesh network and the tree network, a packet generated by a processing unit, of a processing system having plural processing units, at a starting point to a destination point for another processing unit of the processing system and configured to selectively inject the packet into one of the mesh network and the tree network to transmit the packet to the other processing unit.

公开(公告)号：US10181176B2

公开(公告)日：2019-01-15

申请号：US15420463

申请日：2017-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Santosh Abraham ,  Karthik Ramani ,  Woong Seo ,  Kwontaek Kwon ,  Jeongae Park

IPC: G06T1/60 ,  H04N19/426 ,  H04N19/44 ,  G06T15/04 ,  G06T15/00

Abstract: A texture cache architecture includes a first texture cache to store compressed texel data and a second texture cache to store decompressed texel data. A controller schedules accesses to access texel data from the first or second texture cache. The second texture cache permits decompressed texel data to be reused for more than one texel access request.

公开(公告)号：US10169839B2

公开(公告)日：2019-01-01

申请号：US15098638

申请日：2016-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changmoo Kim ,  Yeongon Cho ,  Soojung Ryu ,  Woong Seo

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: A method of executing a graphics pipeline includes calculating, while executing the graphics pipeline on a current frame, a resource for processing properties of an object included in a following frame, determining, based on a result of the calculating, whether to perform a pre-process for the object included in the following frame, performing the pre-processing, when the pre-process is determined to be performed, comprising transforming the properties of the object that are to be processed in a graphics pipeline for the following frame, and executing, when the pre-process is to be performed, the graphics pipeline for the following frame by using the transformed properties of the object.

公开(公告)号：US10120833B2

公开(公告)日：2018-11-06

申请号：US14165881

申请日：2014-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woong Seo ,  Yeon-Gon Cho ,  Soo-Jung Ryu

IPC: G06F15/80 ,  G06F9/38 ,  G06F9/30

Abstract: Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.

公开(公告)号：US09852070B2

公开(公告)日：2017-12-26

申请号：US14692828

申请日：2015-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woong Seo ,  Sangheon Lee ,  Soojung Ryu ,  Yeongon Cho

IPC: G06F12/0802 ,  G06F12/0864 ,  G06F12/121

CPC classification number: G06F12/0802 ,  G06F12/0864 ,  G06F12/121 ,  G06F2212/1044 ,  G06F2212/604

Abstract: A cache memory apparatus includes a tag comparator configured to compare upper bits of each of pieces of tag data included in a set indicated by a set address that is received with upper bits of a tag address that is received, compare other bits of each of the pieces of the tag data with other bits of the tag address, and determine whether there is a cache hit or a cache miss based on results of the comparisons, and an update controller configured to, in response to the cache miss, determine, as an update candidate, a piece of cache data included in the set and corresponding to the pieces of the tag data, based on the result of the comparison of the upper bits of each of the pieces of the tag data and the upper bits of the tag address, and update the update candidate with new data.

公开(公告)号：US09645855B2

公开(公告)日：2017-05-09

申请号：US14276522

申请日：2014-05-13

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： Woong Seo ,  Yeon-Gon Cho ,  Soo-Jung Ryu ,  Seok-Woo Song ,  John Dongjun Kim ,  Min-Seok Lee

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/505 ,  G06F9/46 ,  G06F9/4881 ,  G06F2209/5022

Abstract: An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.

公开(公告)号：US10515432B2

公开(公告)日：2019-12-24

申请号：US15618685

申请日：2017-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woong Seo ,  Santosh George Abraham

IPC: G06T1/60 ,  G06T1/20 ,  G06T15/00

Abstract: A method of managing graphics data in a graphics processing device may include: receiving a first draw call having a first identifier, generating a first lookup table having the first identifier mapped in association with a first handle value by allocating the first handle value to the first identifier, generating a second lookup table having the first handle value mapped in association with a first graphics state setting value by allocating the first handle value to the first graphics state setting value, wherein the first graphics state setting value corresponds to the first identifier, and performing at least one graphics pipeline operation to process the first draw call by using the first graphics state setting value obtained from the second lookup table.

公开(公告)号：US10255182B2

公开(公告)日：2019-04-09

申请号：US15019368

申请日：2016-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namhyung Kim ,  Junwhan Ahn ,  Kiyoung Choi ,  Woong Seo

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0862

Abstract: A method of managing a cache includes storing first data of an upper level cache in a lower level cache, predicting a reuse distance level of second data having a same signature as the first data based on access information about the first data, and storing the second data in one of the lower level cache and a main memory based on the predicted reuse distance level of the second data.