公开(公告)号：US11056461B2

公开(公告)日：2021-07-06

申请号：US16748138

申请日：2020-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonho Jang ,  Gwangjae Jeon ,  Dongkyu Kim ,  Jungho Park ,  Seokhyun Lee

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78

Abstract: Provided is a method of manufacturing a semiconductor package including providing a carrier substrate, providing sacrificial layer on the carrier substrate, the sacrificial layer including a first sacrificial layer and a second sacrificial layer, providing a redistribution wiring layer on the sacrificial layer, providing a plurality of semiconductor chips on the redistribution wiring layer, providing a mold layer provided on the sacrificial layer, the redistribution wiring layer, and the plurality of semiconductor chips, detaching the first sacrificial layer from the second sacrificial layer, and dicing the second sacrificial layer, the redistribution wiring layer, and the mold layer, wherein a diameters of the first sacrificial layer and the second sacrificial layer are respectively less than a diameter of the carrier substrate, and a diameter of the mold layer is greater than the diameter of the redistribution wiring layer and less than the diameter of the first sacrificial layer.

公开(公告)号：US20240096773A1

公开(公告)日：2024-03-21

申请号：US18319135

申请日：2023-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Kyounglim Suk ,  Yeonho Jang ,  Hyeonjeong Hwang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05093 ,  H01L2224/13008 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/16227 ,  H01L2924/1434

Abstract: A semiconductor package includes a redistribution structure in which at least one redistribution layer and at least one insulating layer are alternately stacked; a semiconductor chip electrically connected to the at least one redistribution layer; and bumps on the redistribution structure, wherein the redistribution structure includes vias extending from the at least one redistribution layer in a vertical stacking direction of the redistribution structure; and under bump metallurgy (UBM) structures electrically connected between the vias and the bumps and configured to face the bumps in the vertical stacking direction of the redistribution structure, wherein each of the UBM structures includes a first UBM layer including a first metal material or an alloy of the first metal material; and a second UBM layer between one of the bumps and the first UBM layer and including a second metal material.

公开(公告)号：US20240088055A1

公开(公告)日：2024-03-14

申请号：US18368309

申请日：2023-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyung SONG ,  Jaegwon Jang ,  Yeonho Jang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/544 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/20 ,  H01L25/105 ,  H01L24/16 ,  H01L2223/54426 ,  H01L2224/16227 ,  H01L2224/21

Abstract: A semiconductor package includes a base structure having a fan-in area and fan-out areas surrounding the fan-in area, a semiconductor chip in the fan-in area, a package body layer in the fan-in area and the fan-out areas and covering the semiconductor chip, a redistribution structure on the package body layer, and alignment marks on the redistribution structure in a plan view. Each of the alignment marks includes a plurality of metal layers, and a plurality of auxiliary patterns are in the redistribution structure under the alignment marks to assist in recognition of the alignment marks.

公开(公告)号：US11791295B2

公开(公告)日：2023-10-17

申请号：US16795733

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gwangjae Jeon ,  Dongkyu Kim ,  Jung-Ho Park ,  Yeonho Jang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498

CPC classification number: H01L24/11 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/04105

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.

公开(公告)号：US11616051B2

公开(公告)日：2023-03-28

申请号：US17239956

申请日：2021-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package device includes a first semiconductor package, a second semiconductor package, and first connection terminals between the first and second semiconductor packages. The first semiconductor package includes a lower redistribution substrate, a semiconductor chip, and an upper redistribution substrate vertically spaced apart from the lower redistribution substrate across the semiconductor chip. The upper redistribution substrate includes a dielectric layer, redistribution patterns vertically stacked in the dielectric layer and each including line and via parts, and bonding pads on uppermost redistribution patterns. The bonding pads are exposed from the dielectric layer and in contact with the first connection terminals. A diameter of each bonding pad decreases in a first direction from a central portion at a top surface of the upper redistribution substrate to an outer portion at the top surface thereof. A thickness of each bonding pad increases in the first direction.

公开(公告)号：US11456241B2

公开(公告)日：2022-09-27

申请号：US16884212

申请日：2020-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Jongyoun Kim ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L23/498 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.

公开(公告)号：US20210407940A1

公开(公告)日：2021-12-30

申请号：US17474614

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Jungho Park ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L25/065

Abstract: A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.