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    Antenna module and device including same
    1.
    发明授权
    Antenna module and device including same 有权

    公开(公告)号：US12218407B2

    公开(公告)日：2025-02-04

    申请号：US17946688

    申请日：2022-09-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Juneseok Lee ,  Youngsub Kim ,  Sanghoon Park ,  Jungho Park ,  Kwanghyun Baek ,  Youngju Lee ,  Jungyub Lee ,  Dohyuk Ha ,  Jinsu Heo

    IPC: H01Q1/22 ,  H01Q1/24 ,  H01Q1/38

    Abstract: The disclosure relates to a pre-5th-Generation (5G) or 5G communication system for supporting higher data rates Beyond 4th-Generation (4G) communication system, such as long term evolution (LTE). An antenna device is provided. The antenna device includes a first printed circuit board (PCB), a second PCB for a plurality of antenna elements, and a radio frequency integrated circuit (RFIC) coupled through a first surface of the first PCB. The second PCB may include a radio frequency (RF) routing layer including RF lines for the respective plurality of antenna elements. The first PCB may include a feeding structure for connecting the RF routing layer and the RFIC. The second PCB may be electrically connected to a second surface of the first PCB opposite to the first surface of the first PCB, through a first surface of the second PCB. The second PCB may be coupled to the plurality of antenna elements.

    Semiconductor package and method of manufacturing the same
    2.
    发明授权
    Semiconductor package and method of manufacturing the same 有权

    公开(公告)号：US11637081B2

    公开(公告)日：2023-04-25

    申请号：US17474614

    申请日：2021-09-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongyoun Kim ,  Jungho Park ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

    IPC: H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L25/065

    Abstract: A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

    Semiconductor package and method of manufacturing the same
    3.
    发明授权
    Semiconductor package and method of manufacturing the same 有权

    公开(公告)号：US11569157B2

    公开(公告)日：2023-01-31

    申请号：US16946209

    申请日：2020-06-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yeonho Jang ,  Jongyoun Kim ,  Jungho Park ,  Jaegwon Jang

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

    Abstract: A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

    Wafer level package
    4.
    发明授权
    Wafer level package 有权

    公开(公告)号：US11264354B2

    公开(公告)日：2022-03-01

    申请号：US16869988

    申请日：2020-05-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinwoo Park ,  Jungho Park ,  Dahye Kim ,  Minjun Bae

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

    Abstract: Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.

    Wafer level package
    6.
    发明授权
    Wafer level package 有权

    公开(公告)号：US11894338B2

    公开(公告)日：2024-02-06

    申请号：US17592947

    申请日：2022-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinwoo Park ,  Jungho Park ,  Dahye Kim ,  Minjun Bae

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

    CPC classification number: H01L24/94 ,  H01L23/3121 ,  H01L24/14 ,  H01L25/0657

    Abstract: Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.

    DISPLAY MODULE PACKAGE
    7.
    发明申请
    DISPLAY MODULE PACKAGE 有权

    公开(公告)号：US20220199880A1

    公开(公告)日：2022-06-23

    申请号：US17693704

    申请日：2022-03-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dahye Kim ,  Seokhyun Lee ,  Jungho Park

    IPC: H01L33/62 ,  H01L33/48 ,  H01L33/56

    Abstract: A display module package includes a semiconductor chip, a wiring member disposed on the semiconductor chip, including an insulating layer and a wiring layer, and contacting at least a portion of the semiconductor chip, a light emitting device array disposed on the wiring member and including a plurality of light emitting devices disposed on one surface, wherein the wiring member is between the semiconductor chip and the light emitting device, and a molding member disposed on the wiring member, sealing part of the light emitting device array, and having an opening for exposing the plurality of light emitting devices.

    Method of manufacturing fan-out wafer level package
    9.
    发明授权
    Method of manufacturing fan-out wafer level package 有权

    公开(公告)号：US11056461B2

    公开(公告)日：2021-07-06

    申请号：US16748138

    申请日：2020-01-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yeonho Jang ,  Gwangjae Jeon ,  Dongkyu Kim ,  Jungho Park ,  Seokhyun Lee

    IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78

    Abstract: Provided is a method of manufacturing a semiconductor package including providing a carrier substrate, providing sacrificial layer on the carrier substrate, the sacrificial layer including a first sacrificial layer and a second sacrificial layer, providing a redistribution wiring layer on the sacrificial layer, providing a plurality of semiconductor chips on the redistribution wiring layer, providing a mold layer provided on the sacrificial layer, the redistribution wiring layer, and the plurality of semiconductor chips, detaching the first sacrificial layer from the second sacrificial layer, and dicing the second sacrificial layer, the redistribution wiring layer, and the mold layer, wherein a diameters of the first sacrificial layer and the second sacrificial layer are respectively less than a diameter of the carrier substrate, and a diameter of the mold layer is greater than the diameter of the redistribution wiring layer and less than the diameter of the first sacrificial layer.

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