公开(公告)号：US11205471B2

公开(公告)日：2021-12-21

申请号：US16935712

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Sangwan Nam

IPC: G11C16/04 ,  G11C11/408 ,  G11C5/02 ,  G11C11/409 ,  G11C5/06 ,  G11C11/4074

Abstract: A memory device includes a memory cell array including cell strings, respectively connected between string select lines and ground select lines, and wordlines connected to memory cells, a control logic to generate a first voltage provided to the string select lines, and a second voltage provided to the ground select lines, and to adjust voltage levels of the first and second voltages to control a channel boosting level of the cell strings, and a row decoder to provide a read voltage, a read pass voltage, and the first and second voltages to the memory cell array under control of the control logic. The control logic generates one of the first and second voltage as a pre-pulse voltage. The row decoder provides a third voltage to at least one of the wordlines.

公开(公告)号：US11043274B2

公开(公告)日：2021-06-22

申请号：US16851622

申请日：2020-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jae-Duk Yu ,  Kang-Bin Lee ,  Sang-Won Shim ,  Bongsoon Lim

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/04 ,  G11C7/10 ,  G11C7/22 ,  G11C16/26

Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.

公开(公告)号：US20210149598A1

公开(公告)日：2021-05-20

申请号：US16918310

申请日：2020-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jaeduk Yu ,  Sangwan Nam ,  Sangwon Park ,  Daeseok Byeon ,  Bongsoon Lim

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

公开(公告)号：US20250159962A1

公开(公告)日：2025-05-15

申请号：US18670794

申请日：2024-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Chan Song ,  Dohyung Kim ,  Dongsoo Lee ,  Hyeji Lee ,  Philjong Song ,  Yonghyuk Choi

IPC: H01L29/423

Abstract: A semiconductor device includes a substrate having a first active region and a second active region, a first gate conductive pattern that extends conformally in a first recess in the first active region, and a second gate conductive pattern that at least partially fills a second recess in the second active region. The first gate conductive pattern has a first thickness in a horizontal direction on an inner lateral surface of the first recess. The second gate conductive pattern has a second thickness in the horizontal direction on an inner lateral surface of the second recess. The first thickness is less than the second thickness.

公开(公告)号：US12119046B2

公开(公告)日：2024-10-15

申请号：US18045541

申请日：2022-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeduk Yu ,  Yohan Lee ,  Yonghyuk Choi ,  Jiho Cho

IPC: G11C16/34 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4096

Abstract: A nonvolatile memory device having a multi-stack memory block includes: a memory cell array divided into a plurality of memory stacks disposed in a vertical direction; and a control circuit configured to perform a channel voltage equalization operation of the plurality of memory stacks, wherein inter-stack portions are between the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks. The control circuit determines, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks and differently controls setup time points for applying a pass voltage, or recovery time points for applying a ground voltage, to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.

公开(公告)号：US11929118B2

公开(公告)日：2024-03-12

申请号：US17748156

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Yohan Lee ,  Sangwon Park ,  Jaeduk Yu

IPC: G11C16/04 ,  G11C7/10 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/0433 ,  G11C7/1039 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26

Abstract: Provided is a non-volatile memory device including a memory cell array including cell strings each including memory cells and a string select transistor connected to a string select line; a page buffer circuit including page buffers each including a forcing latch configured to store forcing information; and a control logic circuit configured to, during a program operation on a selected word line, control at least two of a first voltage applied to the string select line in a first interval before a bit line forcing operation for transferring the forcing information to the selected cell string, a second voltage applied to the string select line in a second interval in which the bit line forcing operation is performed, and a third voltage applied to the string select line in a third interval after the bit line forcing operation is performed, to be different from each other.

公开(公告)号：US11881272B2

公开(公告)日：2024-01-23

申请号：US18159882

申请日：2023-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Yohan Lee

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511 ,  H10B41/27 ,  H10B43/27

Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.

公开(公告)号：US11797405B2

公开(公告)日：2023-10-24

申请号：US17935502

申请日：2022-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G11C16/10 ,  G06F11/20 ,  G11C16/04 ,  G11C16/08 ,  H10B41/27 ,  H10B43/27

CPC classification number: G06F11/2094 ,  G11C16/0483 ,  G11C16/08 ,  G06F2201/85 ,  H10B41/27 ,  H10B43/27

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US11615855B2

公开(公告)日：2023-03-28

申请号：US17334045

申请日：2021-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Yohan Lee

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11556 ,  H01L27/11582

Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.

公开(公告)号：US11024363B2

公开(公告)日：2021-06-01

申请号：US16810527

申请日：2020-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Bongsoon Lim ,  Jaeduk Yu

IPC: G11C5/02 ,  G11C11/408 ,  G11C11/4094 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04

Abstract: A memory device includes word lines stacked on an upper surface of a substrate, channel structures penetrating through the word lines, and each including channel regions connected to one another in a first direction perpendicular to the upper surface of the substrate, and word-line cuts extending in the first direction and dividing the word lines to blocks. The word lines and the channel structures provide memory cell strings, and each of the memory cell strings include memory cells arranged in the first direction. The memory cells included in at least one of the memory cell strings include a first memory cell and a second memory cell disposed at different positions in the first direction, and the number of bits of data stored in the first memory cell is less than the number of bits of data stored in the second memory cell.