公开(公告)号：US12154616B2

公开(公告)日：2024-11-26

申请号：US18493051

申请日：2023-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon-Joo Eom ,  Seungjun Bae ,  Hye Jung Kwon ,  Young-Ju Kim

IPC: G11C7/14 ,  G11C5/14 ,  G11C7/02 ,  G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/50

Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

公开(公告)号：US11862234B2

公开(公告)日：2024-01-02

申请号：US17457077

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon-Joo Eom ,  Seungjun Bae ,  Hye Jung Kwon ,  Young-Ju Kim

IPC: G11C7/20 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/14 ,  G11C7/02 ,  G11C29/50 ,  G11C11/4072 ,  G11C29/02 ,  G11C7/10 ,  G11C5/14

CPC classification number: G11C11/4093 ,  G11C5/147 ,  G11C7/02 ,  G11C7/1069 ,  G11C7/14 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G11C29/028 ,  G11C29/50 ,  G11C29/021 ,  G11C29/023 ,  G11C2207/2254

Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

公开(公告)号：US11195571B2

公开(公告)日：2021-12-07

申请号：US16136895

申请日：2018-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon-Joo Eom ,  Seungjun Bae ,  Hye Jung Kwon ,  Young-Ju Kim

IPC: G11C11/4093 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/14 ,  G11C7/20 ,  G11C7/02 ,  G11C29/50 ,  G11C11/4072 ,  G11C29/02 ,  G11C7/10 ,  G11C5/14

Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

公开(公告)号：US10361699B2

公开(公告)日：2019-07-23

申请号：US15922332

申请日：2018-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Ha Lee ,  Chang-Kyo Lee ,  Yoon-Joo Eom

IPC: H03K19/00 ,  G11C7/10

Abstract: A memory module includes an external resistor and a plurality of memory devices commonly connected to the external resistor. Each of the memory devices includes a first reception pad and a first transmission pad. The first reception pad is associated with receiving an impedance calibration command and the first transmission pad is associated with transmitting the impedance calibration command. Each of the memory devices transfers the impedance calibration command to a first memory device which is selected as a master among the plurality of memory devices through a ring topology. The first memory device performs an impedance calibration operation, determines a resistance and a target output high level voltage of an output driver in response to the impedance calibration command, and transfers the impedance calibration command to a second memory device after performing the impedance calibration operation.

公开(公告)号：US09030262B2

公开(公告)日：2015-05-12

申请号：US13834132

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Chul Cho ,  Yoon-Joo Eom ,  Young-Jin Jeon ,  Yong-Cheol Bae

IPC: H03F3/04 ,  H03F3/45 ,  G11C5/00

CPC classification number: H03F3/45076 ,  G11C5/00 ,  G11C7/1084 ,  H03F3/45183 ,  H03F2200/372 ,  H03F2203/45702

Abstract: An input receiver circuit including a single-to-differential amplifier and a semiconductor device including the input receiver circuit are disclosed. The input receiver circuit includes a first stage amplifier unit and a second stage amplifier unit. The first stage amplifier unit amplifies a single input signal in a single-to-differential mode to generate a differential output signal, without using a reference voltage. The second stage amplifier unit amplifies the differential output signal in a differential-to-single mode to generate a single output signal.

Abstract translation: 公开了包括单差分放大器和包括输入接收器电路的半导体器件的输入接收器电路。 输入接收机电路包括第一级放大器单元和第二级放大器单元。 第一级放大器单元以单差模式放大单个输入信号以产生差分输出信号，而不使用参考电压。 第二级放大器单元以差分到单个模式放大差分输出信号以产生单个输出信号。