公开(公告)号：US10666467B2

公开(公告)日：2020-05-26

申请号：US16108894

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye Jung Kwon ,  Seungjun Bae ,  Yongjae Lee ,  Young-Sik Kim ,  Young-Ju Kim ,  Suyeon Doo ,  Yoon-Joo Eom

IPC: G11C7/10 ,  H04L25/02 ,  G11C13/00 ,  G11C16/26 ,  G11C11/16

Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.

公开(公告)号：US10255969B2

公开(公告)日：2019-04-09

申请号：US16032837

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Joo Eom ,  Joon-Young Park ,  Yongcheol Bae ,  Won Young Lee ,  Seongjin Jang ,  Junghwan Choi ,  Joosun Choi

IPC: G11C5/06 ,  G11C11/4096 ,  G11C11/4093 ,  G11C7/10

Abstract: A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.

公开(公告)号：US09899075B2

公开(公告)日：2018-02-20

申请号：US14795191

申请日：2015-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Joo Eom ,  Joon-Young Park ,  Yongcheol Bae ,  Won Young Lee ,  Seongjin Jang ,  Junghwan Choi ,  Joosun Choi

IPC: G11C5/06 ,  G11C11/4096 ,  G11C11/4093 ,  G11C7/10

CPC classification number: G11C11/4096 ,  G11C7/1084 ,  G11C11/4093 ,  G11C2207/105

Abstract: A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.

公开(公告)号：US09355706B2

公开(公告)日：2016-05-31

申请号：US14322129

申请日：2014-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Ahn ,  Seungjun Bae ,  Joon-Young Park ,  Yoon-Joo Eom

IPC: G11C7/10 ,  G11C11/4076 ,  G11C7/02 ,  G11C7/22 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G11C7/02 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4093

Abstract: An output circuit includes first and second output drivers. The first output driver is configured to transfer a first data signal directly to an output pad in synchronization with a clock signal. The second output driver is configured to transfer a second data signal directly to the output pad in synchronization with an inversion clock signal. The clock signal and the inversion clock enable multiplexing of the first data signal and the second data signal to provide a multiplexed output data signal.

Abstract translation: 输出电路包括第一和第二输出驱动器。 第一输出驱动器被配置为与时钟信号同步地将第一数据信号直接传送到输出焊盘。 第二输出驱动器被配置为与反相时钟信号同步地将第二数据信号直接传送到输出焊盘。 时钟信号和反相时钟使第一数据信号和第二数据信号复用，从而提供多路输出数据信号。

公开(公告)号：US11721391B2

公开(公告)日：2023-08-08

申请号：US17875865

申请日：2022-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Joo Eom ,  Joon-Young Park ,  Yongcheol Bae ,  Won Young Lee ,  Seongjin Jang ,  Junghwan Choi ,  Joosun Choi

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C7/10

CPC classification number: G11C11/4096 ,  G11C7/1084 ,  G11C11/4093 ,  G11C2207/105

Abstract: An operation method of a semiconductor device is disclosed. The semiconductor device includes separate first and second dies in a package and receives first types of signals through first and second respective channels independent of each other and corresponding to the first and second respective dies. The method includes a step in which when information for controlling internal operations of the first and second dies is first applied to the first die through a first pad, the first die performs the internal operation and also transmits the information to the second die through an internal interface connecting the first die and the second die, and a step in which when the information is transmitted to the second die, the second die performs the internal operation.

公开(公告)号：US11443794B2

公开(公告)日：2022-09-13

申请号：US16289747

申请日：2019-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Joo Eom ,  Joon-Young Park ,  Yongcheol Bae ,  Won Young Lee ,  Seongjin Jang ,  Junghwan Choi ,  Joosun Choi

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C7/10

Abstract: An operation method of a semiconductor device is disclosed. The semiconductor device includes separate first and second dies in a package and receives first types of signals through first and second respective channels independent of each other and corresponding to the first and second respective dies. The method includes a step in which when information for controlling internal operations of the first and second dies is first applied to the first die through a first pad, the first die performs the internal operation and also transmits the information to the second die through an internal interface connecting the first die and the second die, and a step in which when the information is transmitted to the second die, the second die performs the internal operation.

公开(公告)号：US09196325B2

公开(公告)日：2015-11-24

申请号：US14248447

申请日：2014-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Joo Eom ,  Byongmo Moon ,  Yongcheol Bae

IPC: G11C7/10 ,  H03K19/00 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: G11C7/1084 ,  G11C7/1057 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/2272 ,  H03K19/0005

Abstract: An integrated circuit includes a data input such as a data pad for receiving an external data signal input and an on-die termination (ODT) information input for receiving ODT information from an external device. An ODT circuit selectively couples a termination resistor to the data pad based on the ODT information. An input buffer is coupled to the data pad for determining data that is input into the pad using a reference voltage. A reference voltage generator is coupled to the input buffer and generates the reference voltage on the basis of the ODT information.

Abstract translation: 集成电路包括诸如用于接收外部数据信号输入的数据焊盘和输入的用于从外部设备接收ODT信息的芯片上端接（ODT）信息的数据输入。 ODT电路基于ODT信息将终端电阻选择性地耦合到数据焊盘。 输入缓冲器耦合到数据焊盘，用于使用参考电压确定输入到焊盘的数据。 参考电压发生器耦合到输入缓冲器，并基于ODT信息产生参考电压。

公开(公告)号：US20190158320A1

公开(公告)日：2019-05-23

申请号：US16108894

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye Jung Kwon ,  Seungjun Bae ,  Yongjae Lee ,  Young-Sik Kim ,  Young-Ju Kim ,  Suyeon Doo ,  Yoon-Joo Eom

IPC: H04L25/02 ,  G11C13/00 ,  G11C11/16 ,  G11C16/26

Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.

公开(公告)号：US10062430B2

公开(公告)日：2018-08-28

申请号：US15889783

申请日：2018-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Joo Eom ,  Joon-Young Park ,  Yongcheol Bae ,  Won Young Lee ,  Seongjin Jang ,  Junghwan Choi ,  Joosun Choi

IPC: G11C5/06 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C7/1084 ,  G11C11/4093 ,  G11C2207/105

Abstract: A multi channel semiconductor device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.

公开(公告)号：US09742355B2

公开(公告)日：2017-08-22

申请号：US14959195

申请日：2015-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon-Joo Eom ,  Seung-Jun Bae ,  Dae-Sik Moon ,  Joon-Young Park ,  Min-Su Ahn

IPC: H03F3/45 ,  H03D7/14 ,  H03K19/003

CPC classification number: H03D7/1441 ,  H03F3/45183 ,  H03F2203/45051 ,  H03F2203/45466 ,  H03F2203/45674 ,  H03F2203/45702 ,  H03K19/00361

Abstract: A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.