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公开(公告)号：US20240319962A1
公开(公告)日：2024-09-26
申请号：US18736241
申请日：2024-06-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ihor VASYLTSOV , Wooseok Chang , Youngnam Hwang
CPC classification number: G06F7/4988 , G06F1/03 , G06F17/10
Abstract: A processor-implemented data processing method includes: normalizing input data of an activation function comprising a division operation; determining dividend data corresponding to a dividend of the division operation by reading, from a memory, a value of a first lookup table addressed by the normalized input data; determining divisor data corresponding to a divisor of the division operation by accumulating the dividend data; and determining output data of the activation function corresponding to an output of the division operation obtained by reading, from the memory, a value of a second lookup table addressed by the dividend data and the divisor data.
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公开(公告)号：US11881260B2
公开(公告)日：2024-01-23
申请号：US17538235
申请日：2021-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngnam Hwang
CPC classification number: G11C13/004 , G11C7/16 , G11C11/54 , G11C13/0026 , G11C13/0069 , G11C2013/0054
Abstract: A neuromorphic computing device includes first and second memory cell arrays, and an analog-to-digital converting circuit. The first memory cell array includes a plurality of resistive memory cells, generates a plurality of read currents based on a plurality of input signals and a plurality of data, and outputs the plurality of read currents through a plurality of bitlines or source lines. The second memory cell array includes a plurality of reference resistive memory cells and an offset resistor, and outputs a reference current through a reference bitline or a reference source line. The analog-to-digital converting circuit converts the plurality of read currents into a plurality of digital signals based on the reference current. The offset resistor is connected between the reference bitline and the reference source line.
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公开(公告)号：US20230380176A1
公开(公告)日：2023-11-23
申请号：US18102349
申请日：2023-01-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Daewon HA , Kyunghwan LEE , Youngnam Hwang
Abstract: A semiconductor device includes a cell region including a plurality of memory cells, and a peripheral circuit region controlling the plurality of memory cells. Each of the plurality of memory cells includes a first active region and a second active region adjacent to each other, a first channel layer and a second channel layer extending in the first direction, connected to the first active region and the second active region, and separated from each other in the third direction, a first ferroelectric layer and a first gate electrode layer sequentially provided on the first channel layer, and a second ferroelectric layer and a second gate electrode layer sequentially provided on the second channel layer. The first gate electrode layer and the second gate electrode layer are separated from each other in the third direction.
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公开(公告)号：US20220366976A1
公开(公告)日：2022-11-17
申请号：US17538235
申请日：2021-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngnam Hwang
Abstract: A neuromorphic computing device includes first and second memory cell arrays, and an analog-to-digital converting circuit. The first memory cell array includes a plurality of resistive memory cells, generates a plurality of read currents based on a plurality of input signals and a plurality of data, and outputs the plurality of read currents through a plurality of bitlines or source lines. The second memory cell array includes a plurality of reference resistive memory cells and an offset resistor, and outputs a reference current through a reference bitline or a reference source line. The analog-to-digital converting circuit converts the plurality of read currents into a plurality of digital signals based on the reference current. The offset resistor is connected between the reference bitline and the reference source line.
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公开(公告)号：US11176993B2
公开(公告)日：2021-11-16
申请号：US16876563
申请日：2020-05-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-In Kim , Youngnam Hwang
IPC: G11C11/56 , G11C11/4096 , G11C11/4097 , G11C11/408 , G11C11/4074 , G11C11/4091 , G11C14/00 , G11C11/54 , G06N3/063 , G11C13/00 , H01L45/00
Abstract: A neuromorphic processor may include at least a first synapse element. The first synapse element may include a first bit cell and a second bit cell, the first bit cell connected to a first bitline, a first inverted bitline, a first wordline, and a first inverted wordline, and the second bit cell connected to the first bitline, the first inverted bitline, a second wordline, and a second inverted wordline. The first synapse element may be configured to receive a first input through the first wordline, the first inverted wordline, the second wordline, and the second inverted wordline, store a first synapse value in the first bit cell and the second bit cell, perform a calculation operation using the first input and the first synapse value, and output a result of the calculation through the first bitline and the first inverted bitline.
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Patent Agency Ranking
公开(公告)号：US20210117155A1
公开(公告)日：2021-04-22
申请号：US17072692
申请日：2020-10-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ihor VASYLTSOV , Wooseok Chang , Youngnam Hwang
IPC: G06F7/498 , G06F7/499 , G06F17/10 , G11C11/408
Abstract: A processor-implemented data processing method includes: normalizing input data of an activation function comprising a division operation; determining dividend data corresponding to a dividend of the division operation by reading, from a memory, a value of a first lookup table addressed by the normalized input data; determining divisor data corresponding to a divisor of the division operation by accumulating the dividend data; and determining output data of the activation function corresponding to an output of the division operation obtained by reading, from the memory, a value of a second lookup table addressed by the dividend data and the divisor data.
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公开(公告)号：US20140027704A1
公开(公告)日：2014-01-30
申请号：US14044581
申请日：2013-10-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngnam Hwang
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
Abstract: Phase-change memory devices are provided. A phase-change memory device may include a substrate and a conductive region on the substrate. Moreover, the phase-change memory device may include a lower electrode on the conductive region. The lower electrode may include a metal silicide layer on the conductive region, and a metal silicon nitride layer including a resistivity of about 10 to about 100 times that of the metal silicide layer. Moreover, the lower electrode may include a metal oxide layer between the metal silicon nitride layer and the metal silicide layer. The metal oxide layer may include a resistivity that is greater than that of the metal silicide layer and less than the resistivity of the metal silicon nitride layer. The phase-change memory device may also include a phase-change layer and an upper electrode on the lower electrode.
Abstract translation: 提供了相变存储器件。 相变存储器件可以包括衬底和衬底上的导电区域。 此外，相变存储器件可以在导电区域上包括下电极。 下部电极可以在导电区域上包括金属硅化物层，以及包含大约金属硅化物层的约10至约100倍的电阻率的金属氮化硅层。 此外，下电极可以在金属氮化硅层和金属硅化物层之间包括金属氧化物层。 金属氧化物层可以包括大于金属硅化物层的电阻率并且小于金属氮化硅层的电阻率。 相变存储器件还可以包括下电极上的相变层和上电极。
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公开(公告)号：US12277961B2
公开(公告)日：2025-04-15
申请号：US18371696
申请日：2023-09-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngnam Hwang
Abstract: A semiconductor device includes memory cells connected to word lines, bit lines, and one source line, a row decoder connected to the word lines, and a sense amplifier circuit connected to the bit lines. In a program operation for two or more selected memory cells, a reference voltage is applied to the one source line, the sense amplifier circuit inputs a selected voltage to one selected bit line connected to the selected memory cells, and the row decoder inputs, to selected word lines connected to respective ones of the selected memory cells, a first program voltage lower than the reference voltage or a second program voltage higher than the reference voltage. Each of the memory cells includes a ferroelectric layer in which at least one of a polarization direction and a polarization degree changes depending on a voltage input to each of the word lines.
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公开(公告)号：US20240257856A1
公开(公告)日：2024-08-01
申请号：US18371696
申请日：2023-09-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngnam Hwang
CPC classification number: G11C11/2257 , G11C5/063 , G11C11/2255 , G11C11/2273 , G11C11/2275 , H10B51/10 , H10B51/20 , H10B51/40
Abstract: A semiconductor device includes memory cells connected to word lines, bit lines, and one source line, a row decoder connected to the word lines, and a sense amplifier circuit connected to the bit lines. In a program operation for two or more selected memory cells, a reference voltage is applied to the one source line, the sense amplifier circuit inputs a selected voltage to one selected bit line connected to the selected memory cells, and the row decoder inputs, to selected word lines connected to respective ones of the selected memory cells, a first program voltage lower than the reference voltage or a second program voltage higher than the reference voltage. Each of the memory cells includes a ferroelectric layer in which at least one of a polarization direction and a polarization degree changes depending on a voltage input to each of the word lines.
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公开(公告)号：US12039288B2
公开(公告)日：2024-07-16
申请号：US17072692
申请日：2020-10-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ihor Vasyltsov , Wooseok Chang , Youngnam Hwang
CPC classification number: G06F7/4988 , G06F1/03 , G06F17/10
Abstract: A processor-implemented data processing method includes: normalizing input data of an activation function comprising a division operation; determining dividend data corresponding to a dividend of the division operation by reading, from a memory, a value of a first lookup table addressed by the normalized input data; determining divisor data corresponding to a divisor of the division operation by accumulating the dividend data; and determining output data of the activation function corresponding to an output of the division operation obtained by reading, from the memory, a value of a second lookup table addressed by the dividend data and the divisor data.
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