公开(公告)号：US11751378B2

公开(公告)日：2023-09-05

申请号：US17369320

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun Choi ,  Kiseok Lee ,  Seungjae Jung ,  Joongchan Shin ,  Taehyun An ,  Moonyoung Jeong ,  Sangyeon Han

IPC: H10B12/00 ,  H01L29/08

CPC classification number: H10B12/30 ,  H01L29/0847 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.

公开(公告)号：US20230189501A1

公开(公告)日：2023-06-15

申请号：US18165692

申请日：2023-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung KIM ,  Taehyun An ,  Kiseok Lee ,  Yoosang Hwang

IPC: H10B12/00 ,  G11C5/06

CPC classification number: H10B12/30 ,  G11C5/063

Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

公开(公告)号：US11587929B2

公开(公告)日：2023-02-21

申请号：US16880230

申请日：2020-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Taehyun An ,  Kiseok Lee ,  Keunnam Kim ,  Yoosang Hwang

IPC: H01L27/108 ,  G11C5/06

Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

公开(公告)号：US11502084B2

公开(公告)日：2022-11-15

申请号：US16986367

申请日：2020-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan Shin ,  Changkyu Kim ,  Hui-Jung Kim ,  Iljae Shin ,  Taehyun An ,  Kiseok Lee ,  Eunju Cho ,  Hyungeun Choi ,  Sung-Min Park ,  Ahram Lee ,  Sangyeon Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528 ,  H01L21/822

Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

公开(公告)号：US11410951B2

公开(公告)日：2022-08-09

申请号：US17207242

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungeun Choi ,  Eun-Ji Kim ,  Jong-Ho Moon ,  Hyoungyol Mun ,  Han-Sik Yoo ,  Kiseok Lee ,  Seungjae Jung ,  Taehyun An ,  Sangyeon Han ,  Yoosang Hwang

IPC: H01L27/108 ,  G11C11/408 ,  H01L25/065 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/18

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.