公开(公告)号：US09349633B2

公开(公告)日：2016-05-24

申请号：US14563269

申请日：2014-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Ik Kim ,  Sung-Eui Kim ,  Hyoung-Sub Kim ,  Sung-Kwan Choi

IPC: H01L21/768 ,  H01L27/108 ,  H01L49/02

CPC classification number: H01L21/768 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor device includes forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating interlayer on the active pattern of the substrate and the isolation layer, removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess, forming a first contact in the first recess on a first region of the active pattern exposed by the first recess, removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess, and filling the enlarged first recess to form a first spacer that surrounds a sidewall of the first contact.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成隔离层，其中限定有源图案，在衬底的有源图案和隔离层上形成绝缘中间层，去除绝缘层间的部分，活性图案和 所述隔离层形成第一凹部，在由所述第一凹部暴露的所述有源图案的第一区域上的所述第一凹部中形成第一接触，通过执行各向同性蚀刻来去除所述第一凹部中的所述有源图案的部分和所述隔离层 处理，以形成放大的第一凹部，并且填充放大的第一凹部以形成围绕第一接触件的侧壁的第一间隔件。

公开(公告)号：US09634012B2

公开(公告)日：2017-04-25

申请号：US15015651

申请日：2016-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin Park ,  Chan-sic Yoon ,  Ki-Seok Lee ,  Hyeon-Ok Jung ,  Dae-Ik Kim ,  Bong-Soo Kim ,  Yong-Kwan Kim ,  Eun-Jung Kim ,  Se-Myeong Jang ,  Min-su Choi ,  Sung-Hee Han ,  Yoo-Sang Hwang

IPC: H01L21/311 ,  H01L27/108 ,  H01L21/308

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

公开(公告)号：US09318494B2

公开(公告)日：2016-04-19

申请号：US14692789

申请日：2015-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Dae-Ik Kim ,  Young-Seung Cho

IPC: H01L27/10 ,  H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L27/10885 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10888

Abstract: A method of forming a DRAM can include forming a plurality of transistors arranged in a first direction on a substrate and forming a bit line structure that extends in the first direction, where the bit line structure being electrically coupled to the plurality of transistors at respective locations in the first direction. A plurality of first landing pads an be formed at alternating ones of the respective locations having a first position in a second direction on the substrate. A plurality of second landing pads can be formed at intervening ones of the respective locations between the alternating ones of the respective locations, where the intervening ones of the respective locations having a second position in the second direction on the substrate wherein second position is shifted in the second direction relative to the first position.

Abstract translation: 形成DRAM的方法可以包括在衬底上形成沿第一方向布置的多个晶体管，并形成在第一方向上延伸的位线结构，其中位线结构在相应位置处电耦合到多个晶体管 在第一个方向。 多个第一着陆焊盘形成在相应位置的交替的位置处，在衬底上具有第二方向的第一位置。 可以在相应位置的交替位置之间的相应位置的中间位置形成多个第二着陆焊盘，其中相应位置中的中间位置具有在基板上的第二方向上的第二位置，其中第二位置被移动 相对于第一位置的第二方向。

公开(公告)号：US09196620B2

公开(公告)日：2015-11-24

申请号：US14017502

申请日：2013-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Park ,  Dae-Ik Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L29/423 ,  H01L23/485 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L27/10894 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/5222 ,  H01L27/10888 ,  H01L29/4236 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an insulating interlayer over a substrate in a first region, the insulating layer including contact holes exposing a portion of a surface of the substrate, and contact plugs in the contact holes. The contact plugs include a stacked structure of a first barrier metal layer pattern and a first metal layer pattern. The semiconductor device also includes second metal layer patterns directly contacting with the contact plugs and an upper surface of the insulating interlayer. The second metal layer pattern consists is a metal material layer.

Abstract translation: 半导体器件包括在第一区域中的衬底上的绝缘中间层，所述绝缘层包括暴露衬底表面的一部分的接触孔以及接触孔中的接触插塞。 接触插塞包括第一阻挡金属层图案和第一金属层图案的堆叠结构。 半导体器件还包括与接触插塞直接接触的第二金属层图案和绝缘中间层的上表面。 第二金属层图案是金属材料层。

公开(公告)号：US20130299834A1

公开(公告)日：2013-11-14

申请号：US13770573

申请日：2013-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Seok Lee ,  Dae-Ik Kim

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/823431 ,  H01L29/785

Abstract: A semiconductor device may include a plurality of memory cells. The memory cells may be formed with respective fin shaped active regions with respective recesses formed therein. Thicknesses of the fins may be made relatively thicker around the recesses, such as by selective epitaxial growth around the recesses. The additional thicknesses may be asymmetrical so that portions of the fin on one side are larger than an opposite side. Related methods and systems are also disclosed.

Abstract translation: 半导体器件可以包括多个存储单元。 存储单元可以形成有各自的翅片形状的有源区域，其中形成有相应的凹部。 散热片的厚度可以围绕凹部相对较厚，例如通过围绕凹部的选择性外延生长。 附加厚度可以是不对称的，使得一侧的翅片的部分大于相对侧。 还公开了相关方法和系统。