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    Semiconductor device and method of manufacturing the same
    3.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US10797056B2

    公开(公告)日：2020-10-06

    申请号：US16749791

    申请日：2020-01-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jin-A Kim ,  Yong-Kwan Kim ,  Se-Keun Park ,  Joo-Young Lee ,  Cha-Won Koh ,  Yeong-Cheol Lee

    IPC: H01L27/108 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3065

    Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, buried semiconductor layers, a word line, a bit line, buried contacts, and insulation spacers, and a charge storage. The substrate has active regions and field regions. The buried semiconductor layers are buried in the substrate at the active regions. The word line is buried in the substrate and crosses one of the active regions. The bit line is disposed in one of the active regions. The buried contacts are disposed on the active regions and the field regions. The insulation spacers are disposed on the substrate and on a sidewall of the buried contacts, respectively. The charge storage is disposed on one or more of the buried contacts. The buried semiconductor layers contact, respectively, one of the buried contacts and one of the insulation spacers.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200161308A1

    公开(公告)日：2020-05-21

    申请号：US16749791

    申请日：2020-01-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jin-A KIM ,  Yong-Kwan Kim ,  Se-Keun Park ,  Joo-Young Lee ,  Cha-Won Koh ,  Yeong-Cheol Lee

    IPC: H01L27/108

    Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, buried semiconductor layers, a word line, a bit line, buried contacts, and insulation spacers, and a charge storage. The substrate has active regions and field regions. The buried semiconductor layers are buried in the substrate at the active regions. The word line is buried in the substrate and crosses one of the active regions. The bit line is disposed in one of the active regions. The buried contacts are disposed on the active regions and the field regions. The insulation spacers are disposed on the substrate and on a sidewall of the buried contacts, respectively. The charge storage is disposed on one or more of the buried contacts. The buried semiconductor layers contact, respectively, one of the buried contacts and one of the insulation spacers.

    Semiconductor device and method of manufacturing the same
    8.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US10586798B2

    公开(公告)日：2020-03-10

    申请号：US16170665

    申请日：2018-10-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jin-A Kim ,  Yong-Kwan Kim ,  Se-Keun Park ,  Joo-Young Lee ,  Cha-Won Koh ,  Yeong-Cheol Lee

    IPC: H01L27/108 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/285

    Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, word lines, a doped junction, bit line structures, and buried contacts. The substrate has active regions. The word lines extend across the active regions. The doped junction has impurities and is arranged at the active regions, and includes first junctions and second junctions, each first junction arranged at a central portion of one of the active regions and each second junction arranged at an end portion of another one of the active regions, a buried semiconductor layer being included in each second junction. The bit line structures contact with a respective one of the first junctions. The buried contacts are arranged in a matrix shape, each contacting with a respective one of the second junctions and the included buried semiconductor layer and simultaneously contacting with a charge storage for storing data.

    Memory device including selectively disposed landing pads expanded over signal line
    9.
    发明授权
    Memory device including selectively disposed landing pads expanded over signal line 有权
    存储器件包括通过信号线扩展的选择性地布置的着陆焊盘

    公开(公告)号：US09559103B2

    公开(公告)日：2017-01-31

    申请号：US14716594

    申请日：2015-05-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Je-Min Park ,  Tae-Jin Park ,  Yong-Kwan Kim ,  Yoo-Sang Hwang

    IPC: H01L27/108

    CPC classification number: H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894

    Abstract: Provided is a memory device. The memory device includes a substrate including a cell area and a peripheral area; gate line stacks and bit line stacks configured to vertically cross in the cell area; buried contacts disposed in areas, which are simultaneously shared by neighboring gate line stacks and neighboring bit line stacks; expanded landing pads including expanded portions connected to the buried contacts and expanded over adjacent bit line stacks, and disposed in a row; landing pads spaced apart from the expanded landing pads as a column, connected to the buried contacts, and having horizontal widths smaller than those of the expanded landing pads; and first storage nodes connected to the expanded portions of the expanded landing pads, and second storage nodes connected to the landing pads.

    Abstract translation: 提供了一种存储器件。 存储装置包括：基板，包括单元区域和周边区域; 栅极线堆叠和位线堆叠被配置为在单元区域中垂直交叉; 埋设的触点设置在由相邻栅极线堆叠和相邻位线堆叠同时共享的区域中; 扩展的着陆焊盘，包括连接到埋入触点的扩展部分，并在相邻位线堆叠上扩展，并且布置成一排; 与扩展的着陆焊盘间隔开的着陆焊盘作为柱，连接到埋置的触点，并且具有比扩展的焊盘的水平宽度小的水平宽度; 以及连接到扩展的着陆焊盘的扩展部分的第一存储节点，以及连接到着陆焊盘的第二存储节点。

    METHOD OF FORMING ACTIVE PATTERNS, ACTIVE PATTERN ARRAY, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD OF FORMING ACTIVE PATTERNS, ACTIVE PATTERN ARRAY, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
    形成活动图案的方法，活性图案阵列和制造半导体器件的方法

    公开(公告)号：US20170025420A1

    公开(公告)日：2017-01-26

    申请号：US15015651

    申请日：2016-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae-Jin Park ,  Chan-sic Yoon ,  Ki-Seok Lee ,  Hyeon-Ok Jung ,  Dae-Ik Kim ,  Bong-Soo Kim ,  Yong-Kwan Kim ,  Eun-Jung Kim ,  Se-Myeong Jang ,  Min-su Choi ,  Sung-Hee Han ,  Yoo-Sang Hwang

    IPC: H01L27/108 ,  H01L21/308

    CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

    Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

    Abstract translation: 在形成有源图案的方法中，在基板的单元区域上沿第一方向形成第一图案，并且在基板的外围电路区域上形成第二图案。 第一图案沿与第一方向交叉的第三方向延伸。 第一掩模在第一图案上沿第一方向形成，第二掩模形成在第二图案上。 第一掩模沿与第三方向交叉的第四方向延伸。 第三掩模形成在沿第四方向延伸的第一掩模之间。 使用第一至第三掩模蚀刻第一和第二图案以形成第三和第四图案。 使用第三和第四图案蚀刻衬底的上部，以在单元和外围电路区域中形成第一和第二有源图案。

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