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    Semiconductor devices
    1.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US10818671B2

    公开(公告)日：2020-10-27

    申请号：US16134252

    申请日：2018-09-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Seok Lee ,  Bomg-Soo Kim ,  Ji-Young Kim ,  Sung-Hee Han ,  Yoo-Sang Hwang

    IPC: H01L27/108 ,  H01L21/764 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

    Abstract: A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

    Memory device including selectively disposed landing pads expanded over signal line
    2.
    发明授权
    Memory device including selectively disposed landing pads expanded over signal line 有权
    存储器件包括通过信号线扩展的选择性地布置的着陆焊盘

    公开(公告)号：US09559103B2

    公开(公告)日：2017-01-31

    申请号：US14716594

    申请日：2015-05-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Je-Min Park ,  Tae-Jin Park ,  Yong-Kwan Kim ,  Yoo-Sang Hwang

    IPC: H01L27/108

    CPC classification number: H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894

    Abstract: Provided is a memory device. The memory device includes a substrate including a cell area and a peripheral area; gate line stacks and bit line stacks configured to vertically cross in the cell area; buried contacts disposed in areas, which are simultaneously shared by neighboring gate line stacks and neighboring bit line stacks; expanded landing pads including expanded portions connected to the buried contacts and expanded over adjacent bit line stacks, and disposed in a row; landing pads spaced apart from the expanded landing pads as a column, connected to the buried contacts, and having horizontal widths smaller than those of the expanded landing pads; and first storage nodes connected to the expanded portions of the expanded landing pads, and second storage nodes connected to the landing pads.

    Abstract translation: 提供了一种存储器件。 存储装置包括：基板，包括单元区域和周边区域; 栅极线堆叠和位线堆叠被配置为在单元区域中垂直交叉; 埋设的触点设置在由相邻栅极线堆叠和相邻位线堆叠同时共享的区域中; 扩展的着陆焊盘，包括连接到埋入触点的扩展部分，并在相邻位线堆叠上扩展，并且布置成一排; 与扩展的着陆焊盘间隔开的着陆焊盘作为柱，连接到埋置的触点，并且具有比扩展的焊盘的水平宽度小的水平宽度; 以及连接到扩展的着陆焊盘的扩展部分的第一存储节点，以及连接到着陆焊盘的第二存储节点。

    METHOD OF FORMING ACTIVE PATTERNS, ACTIVE PATTERN ARRAY, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD OF FORMING ACTIVE PATTERNS, ACTIVE PATTERN ARRAY, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
    形成活动图案的方法，活性图案阵列和制造半导体器件的方法

    公开(公告)号：US20170025420A1

    公开(公告)日：2017-01-26

    申请号：US15015651

    申请日：2016-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae-Jin Park ,  Chan-sic Yoon ,  Ki-Seok Lee ,  Hyeon-Ok Jung ,  Dae-Ik Kim ,  Bong-Soo Kim ,  Yong-Kwan Kim ,  Eun-Jung Kim ,  Se-Myeong Jang ,  Min-su Choi ,  Sung-Hee Han ,  Yoo-Sang Hwang

    IPC: H01L27/108 ,  H01L21/308

    CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

    Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

    Abstract translation: 在形成有源图案的方法中，在基板的单元区域上沿第一方向形成第一图案，并且在基板的外围电路区域上形成第二图案。 第一图案沿与第一方向交叉的第三方向延伸。 第一掩模在第一图案上沿第一方向形成，第二掩模形成在第二图案上。 第一掩模沿与第三方向交叉的第四方向延伸。 第三掩模形成在沿第四方向延伸的第一掩模之间。 使用第一至第三掩模蚀刻第一和第二图案以形成第三和第四图案。 使用第三和第四图案蚀刻衬底的上部，以在单元和外围电路区域中形成第一和第二有源图案。

    Methods for fabricating a semiconductor device
    4.
    发明授权
    Methods for fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09159730B2

    公开(公告)日：2015-10-13

    申请号：US14097786

    申请日：2013-12-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dae-Ik Kim ,  Ho-In Ryu ,  Nak-Jin Son ,  Yoo-Sang Hwang

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888

    Abstract: A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape.

    Abstract translation: 一种用于制造半导体器件的方法包括在衬底上形成器件隔离层图案以形成有源区，所述有源区包括位于有源区的中心p处的第一接触形成区和第二接触形成区 所述有源区，在所述基板上形成绝缘层和第一导电层，在所述第一导电层上形成具有隔离形状的掩模图案，蚀刻所述第一导电层和所述绝缘层，以暴露所述第一触点形成的有源区 通过使用掩模图案形成柱状结构之间的开口部分，在开口中形成第二导电层，图案化第二导电层和第一预导电层图案，以形成与第一接触形成区域接触的布线结构和 具有延长的线形。

    Semiconductor devices having balancing capacitor and methods of forming the same
    5.
    发明授权
    Semiconductor devices having balancing capacitor and methods of forming the same 有权
    具有平衡电容器的半导体器件及其形成方法

    公开(公告)号：US09117696B2

    公开(公告)日：2015-08-25

    申请号：US14077834

    申请日：2013-11-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Un Kim ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

    IPC: H01L21/02 ,  H01L27/108 ,  G11C11/4097 ,  G11C11/4099

    CPC classification number: H01L27/10897 ,  G11C11/4097 ,  G11C11/4099 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

    Abstract: A semiconductor memory device includes a substrate including cell block, a balancing block, and a sense block. A plurality of cell bit lines are formed in the cell block of. A plurality of cell plugs are formed adjacent to side surfaces of the bit lines. Cell inner spacers, air spacers, and cell outer spacers are formed between the cell bit lines and the cell plugs. A plurality of balancing bit lines are formed in the balancing block. A plurality of balancing plugs are formed adjacent to side surfaces of the balancing bit lines. Balancing inner spacers and balancing outer spacers are formed between the balancing bit lines and the balancing plugs. The balancing bit lines and at least some of the cell bit lines are connected to the sense block.

    Abstract translation: 半导体存储器件包括包括单元块，平衡块和感测块的衬底。 在单元块中形成多个单元位线。 在位线的侧面附近形成多个电池插头。 在单元位线和电池插头之间形成电池内隔板，空气间隔件和电池外隔板。 在平衡块中形成多个平衡位线。 在平衡位线的侧表面附近形成多个平衡塞。 在平衡位线和平衡插头之间形成平衡内部间隔件和平衡外部间隔件。 平衡位线和至少一些单元位线连接到感测块。

    Semiconductor devices
    6.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11417665B2

    公开(公告)日：2022-08-16

    申请号：US17060026

    申请日：2020-09-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Seok Lee ,  Bomg-Soo Kim ,  Ji-Young Kim ,  Sung-Hee Han ,  Yoo-Sang Hwang

    IPC: H01L27/108 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/764

    Abstract: A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

    SEMICONDUCTOR DEVICES
    8.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190157275A1

    公开(公告)日：2019-05-23

    申请号：US16134252

    申请日：2018-09-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Seok Lee ,  Bomg-Soo Kim ,  Ji-Young Kim ,  Sung-Hee Han ,  Yoo-Sang Hwang

    IPC: H01L27/108 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

    Abstract: A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09337151B2

    公开(公告)日：2016-05-10

    申请号：US14457185

    申请日：2014-08-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Je-Min Park ,  Yoo-Sang Hwang

    IPC: H01L29/68 ,  H01L21/768 ,  H01L29/94 ,  H01L21/4763 ,  H01L23/538 ,  H01L23/535 ,  H01L27/108

    CPC classification number: H01L23/5386 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate having a contact region. An interlayer insulating layer is disposed on the semiconductor substrate. A lower contact plug passing through the interlayer insulating layer and electrically connected to the contact region is disposed. An interconnection structure is disposed on the interlayer insulating layer. An adjacent interconnection spaced apart from the interconnection structure is disposed on the interlayer insulating layer. A bottom surface of the interconnection structure includes a first part overlapping a part of an upper surface of the lower contact plug, and a second part overlapping the interlayer insulating layer.

    Abstract translation: 提供一种半导体器件。 半导体器件包括具有接触区域的半导体衬底。 层间绝缘层设置在半导体衬底上。 设置穿过层间绝缘层并电连接到接触区域的下接触插塞。 互连结构设置在层间绝缘层上。 与互连结构间隔开的相邻互连设置在层间绝缘层上。 互连结构的底表面包括与下接触插塞的上表面的一部分重叠的第一部分和与层间绝缘层重叠的第二部分。

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