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    Semiconductor devices
    1.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US10818671B2

    公开(公告)日：2020-10-27

    申请号：US16134252

    申请日：2018-09-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Seok Lee ,  Bomg-Soo Kim ,  Ji-Young Kim ,  Sung-Hee Han ,  Yoo-Sang Hwang

    IPC: H01L27/108 ,  H01L21/764 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

    Abstract: A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

    METHOD OF FORMING ACTIVE PATTERNS, ACTIVE PATTERN ARRAY, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD OF FORMING ACTIVE PATTERNS, ACTIVE PATTERN ARRAY, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
    形成活动图案的方法，活性图案阵列和制造半导体器件的方法

    公开(公告)号：US20170025420A1

    公开(公告)日：2017-01-26

    申请号：US15015651

    申请日：2016-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae-Jin Park ,  Chan-sic Yoon ,  Ki-Seok Lee ,  Hyeon-Ok Jung ,  Dae-Ik Kim ,  Bong-Soo Kim ,  Yong-Kwan Kim ,  Eun-Jung Kim ,  Se-Myeong Jang ,  Min-su Choi ,  Sung-Hee Han ,  Yoo-Sang Hwang

    IPC: H01L27/108 ,  H01L21/308

    CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

    Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

    Abstract translation: 在形成有源图案的方法中，在基板的单元区域上沿第一方向形成第一图案，并且在基板的外围电路区域上形成第二图案。 第一图案沿与第一方向交叉的第三方向延伸。 第一掩模在第一图案上沿第一方向形成，第二掩模形成在第二图案上。 第一掩模沿与第三方向交叉的第四方向延伸。 第三掩模形成在沿第四方向延伸的第一掩模之间。 使用第一至第三掩模蚀刻第一和第二图案以形成第三和第四图案。 使用第三和第四图案蚀刻衬底的上部，以在单元和外围电路区域中形成第一和第二有源图案。

    Semiconductor device including a bit line
    3.
    发明授权
    Semiconductor device including a bit line 有权

    公开(公告)号：US10332831B2

    公开(公告)日：2019-06-25

    申请号：US15638552

    申请日：2017-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Augustin Jinwoo Hong ,  Dae-Ik Kim ,  Chan-Sic Yoon ,  Ki-Seok Lee ,  Dong-Min Han ,  Sung-Ho Jang ,  Yoo-Sang Hwang ,  Bong-Soo Kim ,  Je-Min Park

    IPC: H01L27/108 ,  H01L23/522 ,  H01L27/11568 ,  H01L21/768

    Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.

    Semiconductor devices and methods of manufacturing semiconductor devices
    4.
    发明授权
    Semiconductor devices and methods of manufacturing semiconductor devices 有权
    半导体器件和制造半导体器件的方法

    公开(公告)号：US09478548B2

    公开(公告)日：2016-10-25

    申请号：US14639360

    申请日：2015-03-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Do-Yeong Lee ,  Chan-Sic Yoon ,  Ki-Seok Lee ,  Hyeon-Ok Jung

    IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/78 ,  H01L21/28 ,  H01L21/311 ,  H01L21/02 ,  H01L29/423

    CPC classification number: H01L27/10823 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/4236

    Abstract: A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening.

    Abstract translation: 一种制造半导体器件的方法包括在衬底上形成隔离图案以限定其中心部分具有第一接触区域和其边缘部分处的第二和第三接触区域的有源图案。 该方法还包括在隔离图案的上部形成掩埋栅极结构和有源图案，在隔离图案和有源图案上形成第一绝缘层，并蚀刻第一绝缘层的一部分和蚀刻第 第一接触区域以形成暴露第一接触区域的初步开口。 该方法还包括蚀刻隔离图案以形成开口，在开口的侧壁上形成绝缘图案，并且形成与开口中的第一接触区域接触的布线结构。

    Semiconductor memory devices and manufacturing methods thereof
    6.
    发明授权
    Semiconductor memory devices and manufacturing methods thereof 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09443734B2

    公开(公告)日：2016-09-13

    申请号：US14574907

    申请日：2014-12-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ki-Seok Lee ,  Jung-Hwan Park ,  Hyo-Jin Park ,  Kyu-Hyun Lee

    IPC: H01L21/28 ,  H01L29/423 ,  H01L27/108

    CPC classification number: H01L21/28008 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/4236

    Abstract: A semiconductor memory device and a manufacturing method of the semiconductor memory device are provided. The semiconductor memory device can include a substrate in which a cell area and a peripheral area are defined, a first gate insulating layer on the peripheral area, and a poly gate layer on the first gate insulating layer to form a combined stack, wherein the combined stack of the first gate insulating layer and the first poly gate layer is absent from the cell area.

    Abstract translation: 提供半导体存储器件和半导体存储器件的制造方法。 半导体存储器件可以包括其中限定了单元区域和外围区域的基板，外围区域上的第一栅极绝缘层，以及在第一栅极绝缘层上形成组合堆叠的多晶硅栅极层，其中组合 第一栅极绝缘层和第一多晶硅层的堆叠不存在于电池区域中。

    Semiconductor devices
    7.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11417665B2

    公开(公告)日：2022-08-16

    申请号：US17060026

    申请日：2020-09-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Seok Lee ,  Bomg-Soo Kim ,  Ji-Young Kim ,  Sung-Hee Han ,  Yoo-Sang Hwang

    IPC: H01L27/108 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/764

    Abstract: A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

    Apparatus and method for detecting counterfeit advertiser in wireless communication system
    8.
    发明授权
    Apparatus and method for detecting counterfeit advertiser in wireless communication system 有权

    公开(公告)号：US10728128B2

    公开(公告)日：2020-07-28

    申请号：US16447233

    申请日：2019-06-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-Kyu Choi ,  Sin-Seok Seo ,  Ki-Seok Lee ,  Do-Hy Hong

    IPC: H04L12/28 ,  H04L12/26 ,  H04W12/12 ,  H04W4/80 ,  H04W84/18 ,  H04W12/00

    Abstract: The present disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for internet of things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method for detecting a counterfeit advertiser by a server includes detecting a random delay time or a cumulative interval for a reference device based on a time stamp for an advertisement packet received from the reference device, and detecting a random delay time or a cumulative interval for a receiving device other than the reference device based on a time stamp for an advertisement packet received from the receiving device.

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