公开(公告)号：US20170025420A1

公开(公告)日：2017-01-26

申请号：US15015651

申请日：2016-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin Park ,  Chan-sic Yoon ,  Ki-Seok Lee ,  Hyeon-Ok Jung ,  Dae-Ik Kim ,  Bong-Soo Kim ,  Yong-Kwan Kim ,  Eun-Jung Kim ,  Se-Myeong Jang ,  Min-su Choi ,  Sung-Hee Han ,  Yoo-Sang Hwang

IPC: H01L27/108 ,  H01L21/308

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

Abstract translation: 在形成有源图案的方法中，在基板的单元区域上沿第一方向形成第一图案，并且在基板的外围电路区域上形成第二图案。 第一图案沿与第一方向交叉的第三方向延伸。 第一掩模在第一图案上沿第一方向形成，第二掩模形成在第二图案上。 第一掩模沿与第三方向交叉的第四方向延伸。 第三掩模形成在沿第四方向延伸的第一掩模之间。 使用第一至第三掩模蚀刻第一和第二图案以形成第三和第四图案。 使用第三和第四图案蚀刻衬底的上部，以在单元和外围电路区域中形成第一和第二有源图案。

公开(公告)号：US09634012B2

公开(公告)日：2017-04-25

申请号：US15015651

申请日：2016-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin Park ,  Chan-sic Yoon ,  Ki-Seok Lee ,  Hyeon-Ok Jung ,  Dae-Ik Kim ,  Bong-Soo Kim ,  Yong-Kwan Kim ,  Eun-Jung Kim ,  Se-Myeong Jang ,  Min-su Choi ,  Sung-Hee Han ,  Yoo-Sang Hwang

IPC: H01L21/311 ,  H01L27/108 ,  H01L21/308

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

公开(公告)号：US09972527B2

公开(公告)日：2018-05-15

申请号：US15263822

申请日：2016-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Eun Kim ,  Yong-Kwan Kim ,  Se-Myeong Jang ,  Yoo-Sang Hwang ,  Bong-Soo Kim

IPC: H01L21/00 ,  H01L21/768 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108 ,  G11C11/406

CPC classification number: H01L21/7682 ,  G11C11/40615 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4091 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10885 ,  H01L28/00

Abstract: A semiconductor device includes a substrate including a plurality of active areas. A conductive pattern is in contact with an active area. First and second conductive line structures face first and second side walls of the conductive pattern. An air spacer is disposed between the first and second side walls. The first and second conductive line structures include a conductive line and a conductive line mask layer. The conductive line mask layer includes a lower portion having a first width and an upper portion having a second width narrower than the first width. The air spacer includes a first air spacer disposed on a side wall of the lower portion of the conductive line mask layer and a second air spacer disposed on a side wall of the upper portion of the conductive line mask layer. The second air spacer is connected with the first air spacer.

公开(公告)号：US20170154805A1

公开(公告)日：2017-06-01

申请号：US15263822

申请日：2016-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNG-EUN KIM ,  Yong-Kwan Kim ,  Se-Myeong Jang ,  Yoo-Sang Hwang ,  Bong-Soo Kim

IPC: H01L21/768 ,  H01L23/522 ,  G11C11/4091 ,  H01L23/532 ,  G11C11/406 ,  G11C11/408 ,  H01L27/108 ,  H01L23/528

CPC classification number: H01L21/7682 ,  G11C11/40615 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4091 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10885 ,  H01L28/00

Abstract: A semiconductor device includes a substrate including a plurality of active areas. A conductive pattern is in contact with an active area. First and second conductive line structures face first and second side walls of the conductive pattern. An air spacer is disposed between the first and second side walls. The first and second conductive line structures include a conductive line and a conductive line mask layer. The conductive line mask layer includes a lower portion having a first width and an upper portion having a second width narrower than the first width. The air spacer includes a first air spacer disposed on a side wall of the lower portion of the conductive line mask layer and a second air spacer disposed on a side wall of the upper portion of the conductive line mask layer. The second air spacer is connected with the first air spacer.