公开(公告)号：US20180173447A1

公开(公告)日：2018-06-21

申请号：US15381104

申请日：2016-12-16

Applicant: SanDisk Technologies LLC

Inventor： Henry Chin ,  Sateesh Desireddi ,  Dana Lee ,  Ashwin D T ,  Harshul Gupta ,  Parth Amin ,  Jia Li

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0679 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for dynamic read table generation. One apparatus includes a set of non-volatile storage cells. A controller for a set of non-volatile storage cells is configured to, in response to unsuccessfully reading a storage cell of the set of non-volatile storage cells using a parameter, read the storage cell using one or more shifted values. A controller for a set of non-volatile storage cells is configured to, in response to successfully reading a storage cell using one or more shifted values, add the one or more shifted values to a storage device.

公开(公告)号：US20240321379A1

公开(公告)日：2024-09-26

申请号：US18359816

申请日：2023-07-26

Applicant: SanDisk Technologies LLC

Inventor： Sai Gautham Thoppa ,  Parth Amin ,  Long Pham

IPC: G11C29/46 ,  G11C29/12

CPC classification number: G11C29/46 ,  G11C29/12005 ,  G11C29/12015

Abstract: Non-volatile memory cells are programmed by raising a voltage applied to a selected word line to a program voltage during a first time period of a programming process for selected non-volatile memory cells connected to the selected word line; programming the selected non-volatile memory cells using the program voltage during a second time period after the first time period; testing, during the first time period, whether the voltage applied to the selected word line is greater than one or more intermediate voltages; and elongating the first time period during the first time period if the voltage applied to the selected word line is not greater than one or more of the intermediate voltages.

公开(公告)号：US20240212764A1

公开(公告)日：2024-06-27

申请号：US18355348

申请日：2023-07-19

Applicant: SanDisk Technologies LLC

Inventor： Parth Amin ,  Anubhav Khandelwal ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/14

CPC classification number: G11C16/3445 ,  G11C16/14

Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells disposed in a plurality of planes. The control circuit is configured to concurrently erase a block of memory cells in each of the plurality of planes, determine that the concurrent erase failed, disconnect a first one of the planes from the plurality of planes to form first remaining planes, and concurrently erase a block of memory cells in each of the first remaining planes.

公开(公告)号：US11776628B2

公开(公告)日：2023-10-03

申请号：US17350770

申请日：2021-06-17

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kazuki Isozumi ,  Parth Amin

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459

Abstract: The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.

公开(公告)号：US11545225B1

公开(公告)日：2023-01-03

申请号：US17356823

申请日：2021-06-24

Applicant: SanDisk Technologies LLC

Inventor： Parth Amin ,  Anubhav Khandelwal

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08 ,  G11C11/56

Abstract: A method for detecting a “slow to erase” condition of a non-volatile memory structure, wherein the method comprises initiating an erase/verify memory operation with respect to the memory structure, wherein the erase/verify memory operation comprises applying an erase verify voltage according to an alternating word line scheme; following the erase/verify memory operation, determining if a first bit scan mode criteria is satisfied; and, if the first bit scan mode criteria is satisfied, initiating a read/verify memory operation wherein, the read/verify memory operation comprises applying a read-pass voltage according to an all word line scheme, and a magnitude of the read-pass voltage is greater than a magnitude of the erase verify voltage. Following the read/verify memory operation, the method also comprises determining if a second bit scan mode criteria is satisfied and, if the criteria is not satisfied, designating the memory structure with a fail status.

公开(公告)号：US20220406378A1

公开(公告)日：2022-12-22

申请号：US17350770

申请日：2021-06-17

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kazuki Isozumi ,  Parth Amin

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.

公开(公告)号：US20220399063A1

公开(公告)日：2022-12-15

申请号：US17348261

申请日：2021-06-15

Applicant: SanDisk Technologies LLC

Inventor： Parth Amin ,  Anubhav Khandelwal

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/30 ,  G11C16/04

Abstract: The programming techniques include the step of providing a memory device that includes a plurality of memory cells that are divided into at least two groups including a first group and a second group. The first group includes memory cells that are coupled to full select gate drains (SGDs), and the second group includes memory cells that are coupled to partial SGDs. The method continues with the step of applying a programming voltage to a selected word line that includes at least one memory cell of the first group and at least one memory cell of the second group. Simultaneous to the application of the programming voltage, the method continues with applying voltages to bit lines coupled to memory cells. The voltages being determined based on if the memory cells are of the first group or are of the second group.