-
公开(公告)号：US08713349B2
公开(公告)日：2014-04-29
申请号：US13166094
申请日：2011-06-22
Applicant: Sang Jin Byeon , Jae Bum Ko
Inventor： Sang Jin Byeon , Jae Bum Ko
IPC: G11C5/06
CPC classification number: G11C5/04 , G11C16/20 , G11C2029/4402 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2924/00014
Abstract: A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal.
Abstract translation: 半导体装置可以包括：第一芯片ID生成单元，被配置为通过第一穿通硅通孔接收使能信号和通过第二通过硅通孔的时钟信号，并生成第一芯片ID信号和延迟使能信号; 第二芯片ID生成单元，被配置为通过来自第一芯片ID生成单元的第三通过硅通孔和时钟信号接收延迟使能信号，并生成第二芯片ID信号; 第一芯片选择信号生成单元，被配置为接收第一芯片ID信号和主ID信号，并生成第一芯片选择信号; 以及第二芯片选择信号生成单元，被配置为接收第二芯片ID信号和主ID信号，并生成第二芯片选择信号。
-
公开(公告)号：US08699280B2
公开(公告)日：2014-04-15
申请号：US13339062
申请日：2011-12-28
Applicant: Sang Jin Byeon
Inventor： Sang Jin Byeon
CPC classification number: G11C5/063 , G11C7/1048 , G11C7/1069
Abstract: A semiconductor apparatus includes a normal data line, an auxiliary data line and a data line selection unit. The normal data line is connected with a data selection unit. The auxiliary data line is connected with the data selection unit. The data line selection unit outputs data to one of the normal data line and the auxiliary data line in response to a command signal.
Abstract translation: 半导体装置包括正常数据线，辅助数据线和数据线选择单元。 正常数据线与数据选择单元连接。 辅助数据线与数据选择单元连接。 数据线选择单元响应于命令信号将数据输出到正常数据线和辅助数据线之一。
-
公开(公告)号：US08489902B2
公开(公告)日：2013-07-16
申请号：US12839333
申请日：2010-07-19
Applicant: Jae Bum Ko , Sang Jin Byeon
Inventor： Jae Bum Ko , Sang Jin Byeon
IPC: G06F1/00 , G06F1/12 , H03K19/096 , H03L7/00 , H03H11/16 , H03H11/26 , G11C5/02 , G11C5/06 , G01R13/00 , G01R25/00
CPC classification number: G06F1/10
Abstract: A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic.
Abstract translation: 半导体集成电路包括：被配置为接收外部电压的多个芯片。 每个芯片检测到芯片之一的信号延迟特性，以产生具有与信号延迟特性对应的电平的内部电压。
-
公开(公告)号：US08384447B2
公开(公告)日：2013-02-26
申请号：US13584519
申请日：2012-08-13
Applicant: Sin Hyun Jin , Sang Jin Byeon
Inventor： Sin Hyun Jin , Sang Jin Byeon
IPC: H03L7/00
CPC classification number: H03K17/22 , H01L25/065 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.
Abstract translation: 半导体装置包括被配置为产生上电信号的上电信号生成部，被配置为驱动和输出上电信号的驱动器，以及主电路块，被配置为响应于来自所述上电信号的输出执行预定功能 驱动器，其中所述加电信号产生部分和所述驱动器的输入端子通过可断开元件连接。
-
公开(公告)号：US08344783B2
公开(公告)日：2013-01-01
申请号：US12970623
申请日：2010-12-16
Applicant: Jae Bum Ko , Jong Chern Lee , Sang Jin Byeon
Inventor： Jae Bum Ko , Jong Chern Lee , Sang Jin Byeon
IPC: H03H11/26
CPC classification number: H03K5/1506 , H03K5/05
Abstract: A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal.
Abstract translation: 延迟电路包括：延迟单元，被配置为接收时钟信号，按预定时间间隔顺序地延迟输入信号，并输出多个第一延迟信号; 以及选择单元，被配置为基于一个或多个选择信号来选择所述多个第一延迟信号中的一个，并输出第二延迟信号。
-
Patent Agency Ranking
公开(公告)号：US08274316B2
公开(公告)日：2012-09-25
申请号：US12651018
申请日：2009-12-31
Applicant: Sin Hyun Jin , Sang Jin Byeon
Inventor： Sin Hyun Jin , Sang Jin Byeon
IPC: H03L7/00
CPC classification number: H03K17/22 , H01L25/065 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.
Abstract translation: 半导体装置包括被配置为产生上电信号的上电信号生成部，被配置为驱动和输出上电信号的驱动器，以及主电路块，被配置为响应于来自所述上电信号的输出执行预定功能 驱动器，其中所述加电信号产生部分和所述驱动器的输入端子通过可断开元件连接。
-
公开(公告)号：US08179737B2
公开(公告)日：2012-05-15
申请号：US12431981
申请日：2009-04-29
Applicant: Sang Jin Byeon
Inventor： Sang Jin Byeon
IPC: G11C5/04
CPC classification number: G11C5/147 , G11C7/1045
Abstract: A semiconductor memory apparatus includes an internal circuit configured to be driven by current flowing between first and second voltage nodes, and a current control unit configured to control an amount of the current in response to an operational-speed information signal.
Abstract translation: 一种半导体存储装置，包括被配置为由在第一和第二电压节点之间流动的电流驱动的内部电路，以及被配置为响应于操作速度信息信号来控制电流量的电流控制单元。
-
公开(公告)号：US20110241763A1
公开(公告)日：2011-10-06
申请号：US12840212
申请日：2010-07-20
Applicant: Jae Bum Ko , Sang Jin Byeon
Inventor： Jae Bum Ko , Sang Jin Byeon
IPC: H03K19/003
CPC classification number: G11C8/12
Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison.
Abstract translation: 半导体装置包括单独的芯片指定代码设置块，其被配置为响应于多个芯片熔丝信号而生成具有不同代码值的多个独立芯片指定代码或其中至少两个具有相同代码值的单独芯片指定代码; 以及单个芯片激活块，其被配置为响应于所述多个芯片熔丝信号来比较所述多个独立芯片指定代码与芯片选择地址，并且基于所述比较的结果来启用多个单独芯片激活信号中的一个。
-
公开(公告)号：US20110210780A1
公开(公告)日：2011-09-01
申请号：US12839333
申请日：2010-07-19
Applicant: Jae Bum Ko , Sang Jin Byeon
Inventor： Jae Bum Ko , Sang Jin Byeon
IPC: H03L5/00
CPC classification number: G06F1/10
Abstract: A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic.
Abstract translation: 半导体集成电路包括：被配置为接收外部电压的多个芯片。 每个芯片检测到芯片之一的信号延迟特性，以产生具有与信号延迟特性对应的电平的内部电压。
-
公开(公告)号：US20080061856A1
公开(公告)日：2008-03-13
申请号：US11819424
申请日：2007-06-27
Applicant: Sang Jin Byeon
Inventor： Sang Jin Byeon
CPC classification number: G05F1/465
Abstract: An internal voltage generator of a semiconductor integrated circuit includes a first driver that outputs an internal voltage by using an internal reference voltage during an active operation in accordance with a detection signal generated by using an external voltage and an active enable signal activated during an activation mode, and a second driver that outputs an internal voltage by using the internal reference voltage during the active operation in accordance with the active enable signal.
Abstract translation: 半导体集成电路的内部电压发生器包括：第一驱动器，其根据通过使用外部电压产生的检测信号和在激活模式下激活的有效使能信号，在有效操作期间使用内部参考电压来输出内部电压 以及第二驱动器，其根据有效使能信号在有效操作期间通过使用内部基准电压输出内部电压。
-
-
-
-
-
-
-
-
-
Search Results
36
records
(took 0.024 seconds)
