摘要:
A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.
摘要:
A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.
摘要:
A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.
摘要:
A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.
摘要:
A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.
摘要:
In some embodiments of the present invention, methods of forming a tantalum carbon nitride layer include introducing a source gas including a tantalum metal complex onto a substrate, wherein one or more of the ligands of the tantalum metal complex include nitrogen and one or more of the ligands of the tantalum metal complex include carbon; and thermally decomposing the tantalum metal complex to form a tantalum carbon nitride layer on the substrate. In some embodiments, the tantalum metal complex includes Ta(NR1)(NR2R3)3, wherein R1, R2 and R3 are each independently H or a C1-C6 alkyl group. In some embodiments, the tantalum metal complex may be [Ta(═NC(CH3)2C2H5)(N(CH3)2)3]. Methods of forming a gate structure, methods of manufacturing dual gate electrodes and methods of manufacturing a capacitor including tantalum carbon nitride are also provided herein.
摘要翻译:在本发明的一些实施例中,形成氮化钽层的方法包括将包含钽金属络合物的源气体引入到基底上,其中一个或多个钽金属络合物的配体包括氮和一个或多个 钽金属络合物的配体包括碳; 并且在所述衬底上热分解所述钽金属络合物以形成钽碳氮化物层。 在一些实施方案中,钽金属络合物包括Ta(NR 1)3(NR 2 R 3)3, 其中R 1,R 2和R 3各自独立地为H或C 1 -C 3 - 6烷基。 在一些实施方案中,钽金属络合物可以是[Ta(-NC(CH 3)2)2 H 2 H 5, (N(CH 3)2)3)3。 形成栅极结构的方法,制造双栅电极的方法以及制造包括氮化钽的电容器的方法也在本文中提供。
摘要:
A semiconductor device may include a gate structure having a gate insulation layer formed on a substrate, and a gate electrode formed on the gate insulation layer. A composite barrier layer may be formed on the gate structure.
摘要:
According to example embodiments, a nonvolatile memory cell includes a first electrode and a second electrode, a resistance change film between the first electrode and the second electrode, and a first barrier film contacting the second electrode. The resist change film contains oxygen ions and contacts the first electrode. The first barrier film is configured to reduce (and/or block) the outflow of the oxygen ions from the resistance change film.
摘要:
The present invention discloses a method of manufacturing a semiconductor device having an upper capacitor electrode and a node resistor, including depositing a thin film at a first deposition rate on an edge portion of a wafer and at a second deposition rate on a central portion of the wafer to form the upper capacitor electrode and the node resistor, thereby improving step coverage of the upper capacitor electrode while simultaneously improving resistance distribution of the node resistor.