公开(公告)号：US12282681B2

公开(公告)日：2025-04-22

申请号：US17841083

申请日：2022-06-15

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G06F3/06

Abstract: Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

公开(公告)号：US11922055B2

公开(公告)日：2024-03-05

申请号：US17730345

申请日：2022-04-27

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G11C11/22 ,  G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/22

Abstract: Apparatus and method for managing data in a processing system, such as but not limited to a data storage device such as a solid-state drive (SSD). A ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first construction and a second arrangement of FMEs of a different, second construction arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide pointers to point to each of the respective cache lines based on a time sequence of operation of the processor. Data sets can be migrated to the different arrangements by the controller as required based on the different operational characteristics of the respective FME constructions. The FMEs may be non-volatile and read-destructive. Refresh circuitry can be selectively enacted under different operational modes.

公开(公告)号：US20220405208A1

公开(公告)日：2022-12-22

申请号：US17844141

申请日：2022-06-20

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G06F12/0891

Abstract: A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.

公开(公告)号：US11086717B2

公开(公告)日：2021-08-10

申请号：US16670329

申请日：2019-10-31

Applicant: Seagate Technology LLC

Inventor： Mehmet Emin Aklik ,  Antoine Khoueir ,  Ara Patapoutian ,  Colin Hill ,  Kurt Walter Getreuer ,  Darshana H. Mehta

IPC: G06F11/10 ,  G11C16/04 ,  G11C16/26 ,  H03M13/11 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.

公开(公告)号：US11080129B2

公开(公告)日：2021-08-03

申请号：US16729228

申请日：2019-12-27

Applicant: Seagate Technology LLC

Inventor： Mehmet Emin Aklik ,  Antoine Khoueir ,  Darshana H. Mehta ,  Nicholas Lien

IPC: G06F11/07

Abstract: Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory regions, data loss and/or data recovery processes may be limited to improve drive performance and reliability.

公开(公告)号：US11017864B2

公开(公告)日：2021-05-25

申请号：US16453211

申请日：2019-06-26

Applicant: Seagate Technology LLC

Inventor： Kurt Walter Getreuer ,  Darshana H. Mehta ,  Antoine Khoueir ,  Christopher Joseph Curl

IPC: G06F3/06 ,  G06F12/02 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G01K1/14

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). An initial temperature is stored associated with the programming of data to memory cells in the NVM. A current temperature associated with the NVM is subsequently measured. At such time that a difference interval between the initial and current temperatures exceeds a selected threshold, a preemptive parametric adjustment operation is applied to the NVM. The operation may include a read voltage calibration, a read voltage increment adjustment, and/or a forced garbage collection operation. The operation results in a new set of read voltage set points for the data suitable for the current temperature, and is carried out independently of any pending read commands associated with the data. The initial temperature can be measured during the programming of the data, or measured during the most recent read voltage calibration operation.

公开(公告)号：US10956064B2

公开(公告)日：2021-03-23

申请号：US16456809

申请日：2019-06-28

Applicant: Seagate Technology LLC

Inventor： Darshana H. Mehta ,  Kurt Walter Getreuer ,  Antoine Khoueir ,  Christopher Joseph Curl

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). A circuit measures programming and reading temperatures for a set of memory cells in the NVM. Error rates are determined for each of the reading operations carried out upon the data stored in the memory cells. A code rate for the NVM is adjusted to maintain a selected error rate for the memory cells. The code rate is adjusted in relation to a cross-temperature differential (CTD) value exceeding a selected threshold. The code rate can include an inner code rate as a ratio of user data bits to the total number of user data bits and error correction code (ECC) bits in each code word written to the NVM, and/or an outer code rate as a strength or size of a parity value used to protect multiple code words.

公开(公告)号：US11868621B2

公开(公告)日：2024-01-09

申请号：US17844174

申请日：2022-06-20

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G06F3/06 ,  G11C29/08

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0679 ,  G11C29/08

Abstract: A data storage system can employ a read destructive memory configured with multiple levels. A non-volatile memory unit can be programmed with a first logical state in response to a first write voltage of a first hysteresis loop by a write controller prior to being programmed to a second logical state in response to a second write voltage of the first hysteresis loop, as directed by the write controller. The first and second logical states may be present concurrently in the non-volatile memory unit and subsequently read concurrently as the first logical state and the second logical state.

公开(公告)号：US20220350523A1

公开(公告)日：2022-11-03

申请号：US17730345

申请日：2022-04-27

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G06F3/06

Abstract: Apparatus and method for managing data in a processing system, such as but not limited to a data storage device such as a solid-state drive (SSD). A ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first construction and a second arrangement of FMEs of a different, second construction arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide pointers to point to each of the respective cache lines based on a time sequence of operation of the processor. Data sets can be migrated to the different arrangements by the controller as required based on the different operational characteristics of the respective FME constructions. The FMEs may be non-volatile and read-destructive. Refresh circuitry can be selectively enacted under different operational modes.

公开(公告)号：US20220343962A1

公开(公告)日：2022-10-27

申请号：US17726864

申请日：2022-04-22

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G11C11/22 ,  G11C17/12 ,  G11C7/10

Abstract: A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. The FMEs can include FeRAM, FeFET or FTJ constructions. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation. The FMEs can be used as a main memory, a cache, a buffer, an OTP, a keystore, etc.