公开(公告)号：US20140219003A1

公开(公告)日：2014-08-07

申请号：US13761975

申请日：2013-02-07

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： David Scott Ebsen ,  Antoine Khoueir ,  Jon D. Trantham

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C7/04 ,  G11C11/56 ,  G11C11/5614 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0035 ,  G11C2211/5641

Abstract: A data storage device may generally be constructed and operated with at least one variable resistance memory cell having a first logic state threshold that is replaced with a second logic state threshold by a controller. The first and second logic states respectively corresponding to a predicted resistance shift that is based upon an operating temperature profile.

Abstract translation: 一般来说，数据存储装置可以用至少一个具有第一逻辑状态阈值的可变电阻存储器单元来构造和操作，该第一逻辑状态阈值由控制器被第二逻辑状态阈值代替。 第一和第二逻辑状态分别对应于基于工作温度分布的预测电阻偏移。

公开(公告)号：US10558392B2

公开(公告)日：2020-02-11

申请号：US15639893

申请日：2017-06-30

Applicant: Seagate Technology LLC

Inventor： David Scott Ebsen ,  Dana Simonson

IPC: G06F3/06

Abstract: Systems and methods presented herein provide a controller that is operable to monitor a plurality of background commands to a storage device over a pre-determined period of time and to determine how often each of the background commands is issued during the pre-determined period of time. The controller is further operable to establish a time interval for each of the background commands, and to issue each of the background commands at their respective time intervals.

公开(公告)号：US20190354498A1

公开(公告)日：2019-11-21

申请号：US15982210

申请日：2018-05-17

Applicant: Seagate Technology LLC

Inventor： David Scott Ebsen ,  Dana Lynn Simonson ,  AbdelHakim Alhussien ,  Erich Franz Haratsch ,  Steven Howe

IPC: G06F13/26 ,  G06F9/48 ,  G06F13/16

Abstract: A memory controller manages memory access operations through a flash memory interface of a memory array of a solid-state storage device connected to a host. The memory controller executes a first memory access operation in the memory array. The first memory access operation has a first priority. The memory controller detects a suspending memory access operation available for execution in the memory array and having a higher priority than the first priority. The detection operation distinguishes between suspending memory access operations and non-suspending memory access operations. The memory controller suspends execution of the first memory access operation in the memory array and executes one or more memory access operations having higher priorities than the first priority and being available for execution in the memory array. The memory controller resumes the execution of the first memory access operation in the memory array.

公开(公告)号：US20190004733A1

公开(公告)日：2019-01-03

申请号：US15639893

申请日：2017-06-30

Applicant: Seagate Technology LLC

Inventor： David Scott Ebsen ,  Dana Simonson

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0673 ,  G06F3/0676 ,  G06F3/0679

Abstract: Systems and methods presented herein provide a controller that is operable to monitor a plurality of background commands to a storage device over a pre-determined period of time and to determine how often each of the background commands is issued during the pre-determined period of time. The controller is further operable to establish a time interval for each of the background commands, and to issue each of the background commands at their respective time intervals.

公开(公告)号：US20160098431A1

公开(公告)日：2016-04-07

申请号：US14506950

申请日：2014-10-06

Applicant: Seagate Technology LLC

Inventor： David Scott Ebsen ,  Ryan James Goss ,  Jeffrey L. Whaley ,  Dana Simonson

IPC: G06F17/30 ,  G06F17/16

CPC classification number: G06F16/219

Abstract: A data object is received from a host and stored on a storage compute device. A first mathematical operation is performed on the data object via the storage compute device. An update from the host is received and stored on the storage compute device. The update data is stored separately from the data object and includes a portion of the data object that has subsequently changed. A second mathematical operation is performed on a changed version of the data object using the update data.

Abstract translation: 从主机接收数据对象并存储在存储计算设备上。 通过存储计算设备对数据对象执行第一数学运算。 来自主机的更新被接收并存储在存储计算设备上。 更新数据与数据对象分开存储，并且包括随后改变的数据对象的一部分。 使用更新数据对数据对象的变更版本执行第二数学运算。

公开(公告)号：US20160077978A1

公开(公告)日：2016-03-17

申请号：US14486201

申请日：2014-09-15

Applicant: Seagate Technology LLC

Inventor： David Scott Ebsen ,  Ryan James Goss ,  Jeffrey L. Whaley ,  Dana Simonson

IPC: G06F12/14

CPC classification number: G06F3/06 ,  G06F3/0611 ,  G06F3/0655 ,  G06F3/0661 ,  G06F3/0679

Abstract: A definition is received of at least one data object and a compute object from a host at a storage compute device. A first key is associated with the at least one data object and a second key is associated with the compute object. A command is received from the host to perform a computation that links the first and second keys. The computation is defined by the compute object and acts on the data object. The computation is performed via the storage compute device using the compute object and the data object in response to the command.

Abstract translation: 从存储计算设备的主机接收至少一个数据对象和计算对象的定义。 第一密钥与至少一个数据对象相关联，第二密钥与计算对象相关联。 从主机接收到执行链接第一和第二键的计算的命令。 计算由计算对象定义并作用于数据对象。 响应于该命令，使用计算对象和数据对象通过存储计算设备执行计算。

公开(公告)号：US09076530B2

公开(公告)日：2015-07-07

申请号：US13762033

申请日：2013-02-07

Applicant: Seagate Technology LLC

Inventor： Kevin Arthur Gomez ,  Ryan James Goss ,  Antoine Khoueir ,  David Scott Ebsen ,  Jon D. Trantham

IPC: G11C16/06 ,  G11C16/22 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C16/06 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/22 ,  G11C2207/2245

Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a non-volatile (NV) buffer is adapted to store input write data having a selected logical address. A write circuit is adapted to transfer a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer. A verify circuit is adapted to perform a verify operation at the conclusion of a predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory. The input write data are retained in the NV buffer until successful transfer is verified.

Abstract translation: 用于管理存储器中的数据的方法和装置。 根据一些实施例，非易失性（NV）缓冲器适于存储具有选择的逻辑地址的输入写入数据。 写入电路适于将输入写入数据的副本传送到NV主存储器，同时将存储的输入写入数据保留在NV缓冲器中。 验证电路适于在预定经过时间间隔结束时执行验证操作，以验证输入写入数据的副本成功传送到NV主存储器。 输入写入数据保留在NV缓冲器中，直到验证成功传输。

公开(公告)号：US20140258646A1

公开(公告)日：2014-09-11

申请号：US13789123

申请日：2013-03-07

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Ryan James Goss ,  Mark Allen Gaertner ,  Antoine Khoueir ,  David Scott Ebsen ,  Jon D. Trantham

IPC: G06F12/00

CPC classification number: G11C29/50008 ,  G06F11/10 ,  G06F11/1012 ,  G11C13/00 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0083 ,  G11C2013/0092

Abstract: An incremental signal is defined that includes at least one of a duration and a peak voltage that is less than a respective minimum programming time or minimum programming voltage step of a resistive memory element. A characterization procedure is repeatedly performed that at least involves: applying a signal to the memory element, the signal being incremented by the incremental signal during each subsequent application; measuring a first resistance of the memory element in response to the signal; and c) measuring a second resistance of the memory element after a time period has elapsed from the measurement of the first resistance with no programming signal applied. In response to the first and second resistance measurements of the characterization procedure, a characterization parameter of the memory element is formed.

Abstract translation: 定义增量信号，其包括持续时间和峰值电压中的至少一个小于电阻式存储器元件的相应的最小编程时间或最小编程电压阶跃。 重复执行表征过程，其至少包括：将信号施加到存储元件，在每个随后的应用期间，信号由增量信号递增; 响应于所述信号测量所述存储元件的第一电阻; 以及c）在没有施加编程信号的第一电阻的测量经过一段时间之后测量存储元件的第二电阻。 响应于表征过程的第一和第二电阻测量，形成存储元件的表征参数。

公开(公告)号：US20140244897A1

公开(公告)日：2014-08-28

申请号：US13777868

申请日：2013-02-26

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Ryan James Goss ,  David Scott Ebsen ,  Mark Allen Gaertner

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0238 ,  G06F2212/217 ,  G06F2212/7205 ,  G06F2212/7207

Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, metadata updates are stored in a first tier of a a multi-tier non-volatile memory structure responsive to access operations associated with data objects in the memory structure. The stored metadata updates are logged in a second, lower tier of the memory structure. The stored metadata updates are further migrated to a different location within the first tier responsive to an accumulated count of said access operations.

Abstract translation: 用于管理存储器中的数据的方法和装置。 根据一些实施例，响应于与存储器结构中的数据对象相关联的访问操作，元数据更新被存储在多层非易失性存储器结构的第一层中。 存储的元数据更新记录在内存结构的第二个较低层。 响应于所述访问操作的累积计数，存储的元数据更新进一步迁移到第一层内的不同位置。

公开(公告)号：US20140219034A1

公开(公告)日：2014-08-07

申请号：US13762033

申请日：2013-02-07

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Kevin Arthur Gomez ,  Ryan James Goss ,  Antoine Khoueir ,  David Scott Ebsen ,  Jon D. Trantham

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/22 ,  G11C2207/2245

Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a non-volatile (NV) buffer is adapted to store input write data having a selected logical address. A write circuit is adapted to transfer a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer. A verify circuit is adapted to perform a verify operation at the conclusion of a predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory. The input write data are retained in the NV buffer until successful transfer is verified.

Abstract translation: 用于管理存储器中的数据的方法和装置。 根据一些实施例，非易失性（NV）缓冲器适于存储具有选择的逻辑地址的输入写入数据。 写入电路适于将输入写入数据的副本传送到NV主存储器，同时将存储的输入写入数据保留在NV缓冲器中。 验证电路适于在预定经过时间间隔结束时执行验证操作，以验证输入写入数据的副本成功传送到NV主存储器。 输入写入数据保留在NV缓冲器中，直到验证成功传输。