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公开(公告)号：US10694007B1
公开(公告)日：2020-06-23
申请号：US16372225
申请日：2019-04-01
Applicant: Seagate Technology LLC
Inventor： Jason Vincent Bellorado , Marcus Marrow
Abstract: Systems and methods are disclosed for detection and mitigation of defects within a preamble portion of a signal, such as a data sector preamble recorded to a data storage medium. In certain embodiments, an apparatus may comprise a circuit configured to synchronize a sampling phase for sampling a signal pattern. The circuit may sample a preamble field of the signal pattern to obtain sample values, split the sample values into a plurality of groups, determine defect groups having samples corresponding to defects in the preamble field, remove the defect groups from the plurality of groups, and synchronize the sampling phase based on the plurality of groups.
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公开(公告)号：US10608808B1
公开(公告)日：2020-03-31
申请号：US16134293
申请日：2018-09-18
Applicant: Seagate Technology LLC
Inventor： Jason Vincent Bellorado , Marcus Marrow , Zheng Wu
Abstract: In certain embodiments, a method may include receiving one or more equalized samples of an input signal. The method may further include mitigating one or more excursions in the one or more equalized samples based on one or more current decisions of an iterative decoding process to generate compensated equalized samples. In addition, the method may include performing iterative decoding operations based on the compensated equalized samples, updating the current decisions of the iterative decoding process and outputting the current decisions as a converged result when the iterative decoding operations have converged for the compensated equalized samples.
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Patent Agency Ranking
公开(公告)号：US10483999B1
公开(公告)日：2019-11-19
申请号：US15997571
申请日：2018-06-04
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Vincent Bellorado , Marcus Marrow
Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.
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公开(公告)号：US10382166B1
公开(公告)日：2019-08-13
申请号：US15439450
申请日：2017-02-22
Applicant: Seagate Technology LLC
Inventor： Vincent Brendan Ashe , Jason Vincent Bellorado , Marcus Marrow
Abstract: Systems and methods are disclosed for constrained receiver parameter optimization. Two parameter optimization functions may be applied, with one function providing constraints on the results of the second function in order to determine a parameter set to apply in the receiver. A method may comprise determining a first parameter set based on a first function, determining a second parameter set based on a second function different from the first function, and determining a third parameter set by using the first parameter set to define a subset of a parameter space to which to limit values from the second parameter set. In certain embodiments, a least squares function may be used to constrain the results of a general cost function.
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公开(公告)号：US10152457B1
公开(公告)日：2018-12-11
申请号：US15334167
申请日：2016-10-25
Applicant: Seagate Technology LLC
Inventor： Jason Vincent Bellorado , Marcus Marrow , Zheng Wu
Abstract: An apparatus may include a circuit including a filter configured to update one or more adaptive coefficients of the filter based on an error signal. Further, the circuit may update a constrained coefficient of the filter based on the one or more adaptive coefficients, the constrained coefficient and a desired value. Moreover, the circuit may generate a sample of a sample sequence based on the one or more adaptive coefficients and the updated constrained coefficient, the error signal being based on the sample sequence.
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公开(公告)号：US09998136B1
公开(公告)日：2018-06-12
申请号：US15436709
申请日：2017-02-17
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Vincent Bellorado , Marcus Marrow
CPC classification number: H03M1/18 , G11B20/10027 , G11B20/10037 , G11B20/10222 , H03M1/12 , H03M1/124
Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.
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公开(公告)号：US09954537B1
公开(公告)日：2018-04-24
申请号：US15390453
申请日：2016-12-23
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Kenneth John Evans , Jason Vincent Bellorado
CPC classification number: H03L7/08 , G06F1/022 , H03K5/135 , H03L7/0814
Abstract: In certain embodiments, an apparatus may comprise a circuit configured to scale a phase control value from an external phase control resolution of an external clock frequency to an internal phase control resolution of an internal clock frequency to generate a target phase control value. The circuit may also determine a difference between a current phase control value and the target phase control value and determine a phase step value based on the difference. Further, the circuit may modify a current phase control value based on the phase step value and generate a phase controlled clock signal at the internal clock frequency using the modified phase control value. Additionally, the circuit may divide the phase controlled clock signal at the internal clock frequency to generate a phase controlled clock signal at the external clock frequency.
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