公开(公告)号：US10691190B2

公开(公告)日：2020-06-23

申请号：US15633026

申请日：2017-06-26

Applicant: Seagate Technology LLC

Inventor： Nitin Kumar Chhabra ,  Pritesh Mahadev Pawaskar

IPC: G06F1/3203 ,  G06F30/367 ,  G06F1/3206 ,  G06F1/26 ,  G06F30/20 ,  G06F119/06

Abstract: The disclosed technology provides methods for performing a power delivery network analysis of the memory unit I/O power domain. The methods include performing a signal and power integrity analysis for a memory unit I/O power domain to extract characteristics of a current waveform, determining characteristics of an expected waveform based on a current response for the memory unit I/O power domain, and determining whether the characteristics of the current waveform and the characteristics of the expected waveform are within a tolerance limit. The method also includes various remedial operations and CPM regeneration which may iteratively occur until the waveform matches and final CPM is generated which is use for PDN analysis.

公开(公告)号：US10585817B2

公开(公告)日：2020-03-10

申请号：US15991641

申请日：2018-05-29

Applicant: Seagate Technology LLC

Inventor： Nitin Kumar Chhabra ,  Gaurav Mathur ,  Anant Dalimkar

IPC: G06F17/50 ,  G06F13/16 ,  G01R31/27 ,  G06F11/22

Abstract: A method of testing signal integrity and power integrity in an address bus includes determining a worst case switching scenario for victim bits versus aggressor bits on addresses on the address bus, generating a second switching scenario by eliminating repeated patterns and non-switching patterns for victim bits and aggressor bits, simulating address bus operation with the second switching scenario, and iteratively correlating simulation results with measured results to match simulated results with measured results.

公开(公告)号：US20190199371A1

公开(公告)日：2019-06-27

申请号：US15854222

申请日：2017-12-26

Applicant: Seagate Technology LLC

Inventor： Nitin Kumar Chhabra ,  Rohit Halba ,  Shashi Kumar Shaw ,  Shrikrishna Nana Mehetre

IPC: H03M7/30 ,  H04L25/02 ,  G06F13/42 ,  H03M5/16 ,  H04L27/06

CPC classification number: H03M7/3055 ,  G06F13/426 ,  H03K19/017509 ,  H03K19/018521 ,  H03M5/16 ,  H04L25/0276 ,  H04L25/49 ,  H04L27/06

Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.

公开(公告)号：US20190108301A1

公开(公告)日：2019-04-11

申请号：US15725961

申请日：2017-10-05

Applicant: Seagate Technology LLC

Inventor： Nitin Kumar Chhabra ,  Pritesh Mahadev Pawaskar ,  William Harrison Hempy, II ,  Gaurav Mathur

IPC: G06F17/50

Abstract: A method of generating a chip power model (CPM) for a chip by determining a current profile measurement on a validation board for the chip, and stressing the chip using a plurality of stress factors. A stressed measured waveform is captured and stored. A CPM is generated with the measured waveform captured using the plurality of stress factors. A simulation waveform is captured and stored from the CPM. The measured and simulation waveforms are compared, and when the measured and simulation waveforms do not match, at least one parameter of the CPM is modified iteratively until the measured and simulation waveforms match.