公开(公告)号：US20050105340A1

公开(公告)日：2005-05-19

申请号：US10906069

申请日：2005-02-01

申请人： Shih-Huang Huang

发明人： Shih-Huang Huang

IPC分类号： G11C7/06 ,  G11C16/06 ,  G11C17/12

CPC分类号： G11C17/12 ,  G11C7/065 ,  G11C7/067

摘要： A sensing circuit for sensing logic data is disclosed. A memory cell is electrically connected to a bit line. The sensing circuit includes a first pre-charging module electrically connected to the bit line for pre-charging the bit line. A selecting module is electrically connected between the bit line and a first data line for transmitting signals and for isolating capacitances. A second pre-charging module is electrically connected to the first data line for pre-charging the first data line. A first voltage keeping module is electrically connected to the first data line for maintaining a signal on the first data line at a voltage level. An isolating module is electrically connected between the first data line and a second data line for transmitting signals and for isolating capacitances. A third pre-charging module is electrically connected to the second data line for pre-charging the second data line.

摘要翻译： 公开了一种用于感测逻辑数据的感测电路。 存储单元电连接到位线。 感测电路包括电连接到位线以预充电位线的第一预充电模块。 选择模块电连接在位线和用于传输信号和隔离电容的第一数据线之间。 第二预充电模块电连接到第一数据线，用于对第一数据线进行预充电。 第一电压保持模块电连接到第一数据线，用于将第一数据线上的信号保持在电压电平。 隔离模块电连接在第一数据线和第二数据线之间，用于传输信号和隔离电容。 第三预充电模块电连接到第二数据线，用于对第二数据线进行预充电。

公开(公告)号：US20130010559A1

公开(公告)日：2013-01-10

申请号：US13176858

申请日：2011-07-06

申请人： Shih-Huang Huang

发明人： Shih-Huang Huang

IPC分类号： G11C7/12

CPC分类号： G11C7/062 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/12 ,  G11C7/18

摘要： The invention provides a memory output circuit. The memory output circuit is capable of receiving bit line data and bit bar line data output by a memory cell array. In one embodiment, the memory output circuit comprises a pre-charge circuit, a pre-amplifier circuit, and a sense amplifier. The pre-charge circuit is capable of pre-charging a first node and a first inverse node wherein the bit line data and bit bar line data are respectively output to the first node and the first inverse node. The pre-amplifier circuit is capable of generating a second voltage on a second node and a second inverse voltage on a second inverse node according to a first voltage on the first node and a first inverse voltage on the first inverse node. The sense amplifier is capable of detecting the second voltage on the second node and the second inverse voltage on the second inverse node to generate a third voltage on a third node and a third inverse voltage on a third inverse node.

摘要翻译： 本发明提供一种存储器输出电路。 存储器输出电路能够接收由存储单元阵列输出的位线数据和位线数据。 在一个实施例中，存储器输出电路包括预充电电路，前置放大器电路和读出放大器。 预充电电路能够对第一节点和第一逆节点进行预充电，其中位线数据和位线数据被分别输出到第一节点和第一逆节点。 前置放大器电路能够根据第一节点上的第一电压和第一反向节点上的第一反向电压在第二节点上产生第二电压和第二反向节点上的第二反向电压。 感测放大器能够检测第二节点上的第二电压和第二反向节点上的第二反向电压，以在第三节点上产生第三电压，并在第三反向节点上产生第三反向电压。

公开(公告)号：US06813205B2

公开(公告)日：2004-11-02

申请号：US10604508

申请日：2003-07-28

申请人： Shih-Huang Huang

发明人： Shih-Huang Huang

IPC分类号： G11C700

CPC分类号： H01F19/08 ,  G11C7/065 ,  G11C7/12 ,  H01F17/0033

摘要： A pre-charge and sense out circuit for differential type ROM. The ROM is capable of connecting to either a first bit line or a second bit line. The pre-charge and sense out circuit contains a pre-charging module electrically connected to the first and the second bit lines, for pre-charging the first and the second bit lines; a selecting module electrically connected to the first bit line, the second bit line, a first data line, and a second data line, for transmitting data according to a first control signal; a charge sharing module electrically connected to the first and the second data lines, for sharing electrical charges to the first and the second data lines; and a sensing module electrically connected to the first and the second data lines, for sensing signals on the first and the second data lines so as to generate an output signal.

摘要翻译： 差分型ROM的预充电和感应输出电路。 ROM能够连接到第一位线或第二位线。 预充电和感测输出电路包括电连接到第一和第二位线的预充电模块，用于对第一和第二位线进行预充电; 电连接到第一位线，第二位线，第一数据线和第二数据线的选择模块，用于根据第一控制信号发送数据; 电连接到所述第一数据线和所述第二数据线的电荷共享模块，用于向所述第一和第二数据线共享电荷; 以及电连接到第一和第二数据线的感测模块，用于感测第一和第二数据线上的信号，以产生输出信号。

公开(公告)号：US06490216B1

公开(公告)日：2002-12-03

申请号：US09920162

申请日：2001-08-01

申请人： Juei-Lung Chen ,  Shih-Huang Huang

发明人： Juei-Lung Chen ,  Shih-Huang Huang

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C11/406

摘要： A selective memory refresh circuit for refreshing a memory cell array. The memory cell array has a plurality of word lines connected to a plurality of word line selection circuits for determining if a particular word line needs to be refresh during a refresh cycle. Each word line refresh selection circuit further has a word line address latching device for receiving a word line pre-decode signal, a release signal, a triggering signal and outputting a word line latching signal and a word line refresh compare circuit for receiving the word line pre-decode signal and the word line latching signal and transmitting the result of comparison to a word line driver. When the word line latching signal is at a high level, memory cells attached to the word line are refreshed. On the contrary, when the word line latching signal is at a low level, memory refresh for that word line is skipped.

摘要翻译： 一种用于刷新存储单元阵列的选择性存储器刷新电路。 存储单元阵列具有连接到多个字线选择电路的多个字线，用于确定在刷新周期期间特定字线是否需要刷新。 每个字线刷新选择电路还具有用于接收字线预解码信号，释放信号，触发信号并输出​​字线锁存信号的字线地址锁存装置和用于接收字线的字线刷新比较电路 预解码信号和字线锁存信号，并将比较结果发送到字线驱动器。 当字线锁存信号处于高电平时，附加到字线的存储单元被刷新。 相反，当字线锁存信号处于低电平时，跳过该字线的存储器刷新。

公开(公告)号：US08568147B2

公开(公告)日：2013-10-29

申请号：US12046891

申请日：2008-03-12

申请人： Tsung-Ter Kuo ,  Shih-Huang Huang

发明人： Tsung-Ter Kuo ,  Shih-Huang Huang

IPC分类号： G09B23/00

CPC分类号： G09B23/30

摘要： A tissue mimicking phantom is disclosed, in which the tissue-mimicking phantom comprises: at least an upper gelatin layer, each configured with at least a sunken area; at least a lower gelatin layer, each disposed beneath the at least one upper gelatin layer while being configured with at least a microchannel network having blood-mimicking fluid flowing therein; and at least a micro-heater. By the use of the sunken area of the at least one upper gelatin layer to simulate shapes and depths of different trauma wounds, the healing of anyone of the trauma wounds can be accessed clinically through a physical properties test while subjecting the trauma wound under different negative pressures and different dressings.

摘要翻译： 公开了一种组织模拟体模，其中所述组织模拟体模包括：至少一层上明胶层，每层配置有至少一凹陷区域; 至少一个下部明胶层，每个位于所述至少一个上部明胶层的下面，同时配置有至少一个在其中流动有血液模拟流体的微通道网络; 和至少一个微型加热器。 通过使用至少一个上明胶层的凹陷区域来模拟不同创伤伤口的形状和深度，任何创伤伤口的愈合可以通过物理性能测试临床获得，同时对不同负面的创伤伤口 压力和不同的敷料。

公开(公告)号：US08559212B2

公开(公告)日：2013-10-15

申请号：US13176852

申请日：2011-07-06

申请人： Shih-Huang Huang

发明人： Shih-Huang Huang

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C5/148 ,  G11C7/20 ,  G11C8/08 ,  G11C11/418 ,  G11C2207/2227

摘要： The invention provides a memory circuit. In one embodiment, the memory circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a memory cell array. The first PMOS transistor is coupled between a first voltage terminal and a first node. The second PMOS transistor is coupled between the first voltage terminal and a second node. The first NMOS transistor is coupled between a third node and a second voltage terminal. The second NMOS transistor is coupled between a fourth node and the second voltage terminal. The memory cell array comprises a plurality of memory cells, at least one comprising a first inverter and a second inverter. A positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node.

摘要翻译： 本发明提供一种存储器电路。 在一个实施例中，存储器电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二PMOS晶体管和存储单元阵列。 第一PMOS晶体管耦合在第一电压端子和第一节点之间。 第二PMOS晶体管耦合在第一电压端子和第二节点之间。 第一NMOS晶体管耦合在第三节点和第二电压端子之间。 第二NMOS晶体管耦合在第四节点和第二电压端子之间。 存储单元阵列包括多个存储单元，至少一个存储单元包括第一反相器和第二反相器。 第一反相器的正电源端子耦合到第一节点，第一反相器的负电源端子耦合到第三节点，第二反相器的正电源端子耦合到第二节点，负电源端子 的第二反相器耦合到第四节点。

公开(公告)号：US06871155B2

公开(公告)日：2005-03-22

申请号：US10604472

申请日：2003-07-23

申请人： Shih-Huang Huang

发明人： Shih-Huang Huang

IPC分类号： G01R31/00 ,  G11C7/00 ,  G11C7/06 ,  G11C7/12

CPC分类号： G11C7/067 ,  G11C7/12 ,  G11C2207/005

摘要： A sensing circuit for sensing logic data is shown. A memory cell is electrically connected to a bit line. The sensing circuit contains a first pre-charging module electrically connected to the bit line for pre-charging the bit line. A selecting module is electrically connected between the bit line and a first data line for transmitting signals and for isolating capacitances. A second pre-charging module is electrically connected to the first data line for pre-charging the first data line. A first voltage keeping module is electrically connected to the first data line for maintaining the signal on the first data line at a high voltage level. An isolating module is electrically connected between the first data line and a second data line for transmitting signals and for isolating capacitances. Finally, a third pre-charging module is electrically connected to the second data line for pre-charging the second data line.

摘要翻译： 示出了用于感测逻辑数据的感测电路。 存储单元电连接到位线。 感测电路包含电连接到位线以预充电位线的第一预充电模块。 选择模块电连接在位线和用于传输信号和隔离电容的第一数据线之间。 第二预充电模块电连接到第一数据线，用于对第一数据线进行预充电。 第一电压保持模块电连接到第一数据线，用于将第一数据线上的信号保持在高电压电平。 隔离模块电连接在第一数据线和第二数据线之间，用于传输信号和隔离电容。 最后，第三预充电模块电连接到第二数据线，用于对第二数据线进行预充电。

公开(公告)号：US06553088B1

公开(公告)日：2003-04-22

申请号：US09734626

申请日：2000-12-11

申请人： Juei-Lung Chen ,  Shih-Huang Huang

发明人： Juei-Lung Chen ,  Shih-Huang Huang

IPC分类号： H03D324

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03L7/093

摘要： A digital delay phase locked loop, to quickly perform the phase lock on an input clock signal. The digital delay phase locked circuit has a delay apparatus, a buffer, a phase comparator, an adder-register, a clock divider and a demultiplexer. After a delay operation performed on the input clock signal by the delay apparatus, the phase locked clock signal is output via the buffer. The above two signals are then compared with each other using the phase comparator to output a comparison signal to the adder-register for addition/subtraction delay. Being controlled by the clock divider, the objective of fast phase lock is achieved by the addition/subtraction operation of the demultiplexer.

摘要翻译： 数字延迟锁相环，快速执行输入时钟信号的锁相。 数字延迟锁相电路具有延迟装置，缓冲器，相位比较器，加法器寄存器，时钟分频器和解复用器。 在由延迟装置对输入时钟信号执行延迟操作之后，经由缓冲器输出锁相时钟信号。 然后使用相位比较器将上述两个信号彼此进行比较，以将比较信号输出到加法器寄存器用于加法/减法延迟。 由时钟分频器控制，快速锁相的目的是通过解复用器的加/减操作实现。

公开(公告)号：US06434057B1

公开(公告)日：2002-08-13

申请号：US09682306

申请日：2001-08-16

申请人： Shih-Huang Huang ,  Jui-Lung Chen

发明人： Shih-Huang Huang ,  Jui-Lung Chen

IPC分类号： G11C700

CPC分类号： G11C7/1051

摘要： A memory device has an output buffer. The output buffer is electrically connected to a data output port of a sense amplifier of the memory device for amplifying an output signal from the data output port. The output buffer has a detector for producing a control signal according to the output signal from the data output port, and an amplifier for amplifying the output signal from the data output port. The amplifier has an input port electrically connected to the data output port for accepting the output signal from the data output port, and a control terminal electrically connected to the output terminal of the detector for accepting the control signal from the detector to control operations of the amplifier. When the detector produces the control signal and transmits the control signal to the control terminal of the amplifier, the amplifier begins amplifying the output signal transmitted from the data output port to the input port of the amplifier.

摘要翻译： 存储器件具有输出缓冲器。 输出缓冲器电连接到存储器件的读出放大器的数据输出端口，用于放大来自数据输出端口的输出信号。 输出缓冲器具有根据来自数据输出端口的输出信号产生控制信号的检测器和用于放大来自数据输出端口的输出信号的放大器。 放大器具有电连接到数据输出端口的输入端口，用于接收来自数据输出端口的输出信号，以及控制端子，电连接到检测器的输出端子，用于接收来自检测器的控制信号，以控制 放大器 当检测器产生控制信号并将控制信号发送到放大器的控制端时，放大器开始将从数据输出端口传输到输出端口的输出信号放大。

公开(公告)号：US06414889B1

公开(公告)日：2002-07-02

申请号：US09681989

申请日：2001-07-03

申请人： Jui-Lung Chen ,  Shih-Huang Huang

发明人： Jui-Lung Chen ,  Shih-Huang Huang

IPC分类号： G11C700

CPC分类号： G11C29/12

摘要： A apparatus uses a test method to perform burn-in testing of a static random access memory that has a plurality of word lines, a plurality of first bit lines, a plurality of second bit lines, and a plurality of memory cells for storing data. Each of the memory cells is coupled to a corresponding word line, a corresponding first bit line, a corresponding second bit line, and a power supply that is used to apply a working voltage to the memory cell to drive the memory cell. When the apparatus tests the static random access memory, the apparatus adjusts the working voltage according to a potential of the word lines and voltage gaps between the first bit lines and the second bit lines.

摘要翻译： 一种装置使用测试方法来执行具有多个字线，多个第一位线，多个第二位线和用于存储数据的多个存储器单元的静态随机存取存储器的老化测试。 每个存储器单元耦合到对应的字线，对应的第一位线，相应的第二位线和用于将工作电压施加到存储器单元以驱动存储器单元的电源。 当该装置测试静态随机存取存储器时，该装置根据字线的电位和第一位线与第二位线之间的电压间隙调整工作电压。