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22 条记录 (耗时 0.012 秒)

    Burn-in methods for static random access memories and chips
    2.
    发明授权
    Burn-in methods for static random access memories and chips 有权
    静态随机存取存储器和芯片的老化方法

    公开(公告)号：US07916519B2

    公开(公告)日：2011-03-29

    申请号：US12368218

    申请日：2009-02-09

    申请人： Jui-Lung Chen ,  Wei-Shung Chen ,  Yi-Hsun Chung ,  Chia-Chiuan Chang

    发明人： Jui-Lung Chen ,  Wei-Shung Chen ,  Yi-Hsun Chung ,  Chia-Chiuan Chang

    IPC分类号： G11C11/00

    CPC分类号： G11C29/02 ,  G11C11/41 ,  G11C29/025

    摘要： A burn-in method for SRAMs and chips. For a memory cell of the SRAM, the SRAM burn-in method controls the control signals of the memory cell to generate current paths to pass through the memory cell, the corresponding bit-line and the corresponding bit-line-bar. The contacts/vias in the current paths are tested by providing burn-in currents to flow through the current paths, so that mismatched contacts/vias are burned by the burn-in currents. SRAMs that fail the burn-in test are abandoned after the burn-in procedure.

    摘要翻译： 一种SRAM和芯片的老化方法。 对于SRAM的存储单元，SRAM老化方法控制存储器单元的控制信号，以产生通过存储单元，对应位线和相应位线条的电流路径。 通过提供老化电流流过电流路径来测试电流路径中的触点/通孔，从而使不匹配的触点/通孔被老化电流烧毁。 老化测试失败的SRAM在老化过程之后被放弃。

    BURN-IN METHODS FOR STATIC RANDOM ACCESS MEMORIES AND CHIPS
    3.
    发明申请
    BURN-IN METHODS FOR STATIC RANDOM ACCESS MEMORIES AND CHIPS 有权
    用于静态随机存取存储器和存储器的烧录方法

    公开(公告)号：US20100202219A1

    公开(公告)日：2010-08-12

    申请号：US12368218

    申请日：2009-02-09

    申请人： Jui-Lung Chen ,  Wei-Shung Chen ,  Yi-Hsun Chung ,  Chia-Chiuan Chang

    发明人： Jui-Lung Chen ,  Wei-Shung Chen ,  Yi-Hsun Chung ,  Chia-Chiuan Chang

    IPC分类号： G11C7/00 ,  G11C29/00

    CPC分类号： G11C29/02 ,  G11C11/41 ,  G11C29/025

    摘要： A burn-in method for SRAMs and chips. For a memory cell of the SRAM, the SRAM burn-in method controls the control signals of the memory cell to generate current paths to pass through the memory cell, the corresponding bit-line and the corresponding bit-line-bar. The contacts/vias in the current paths are tested by providing burn-in currents to flow through the current paths, so that mismatched contacts/vias are burned by the burn-in currents. SRAMs that fail the burn-in test are abandoned after the burn-in procedure.

    摘要翻译： 一种SRAM和芯片的老化方法。 对于SRAM的存储单元，SRAM老化方法控制存储器单元的控制信号，以产生通过存储单元，对应位线和相应位线条的电流路径。 通过提供老化电流流过电流路径来测试电流路径中的触点/通孔，从而使不匹配的触点/通孔被老化电流烧毁。 老化测试失败的SRAM在老化过程之后被放弃。

    Semiconductor programmable device
    4.
    发明申请
    Semiconductor programmable device 审中-公开
    半导体可编程器件

    公开(公告)号：US20050104129A1

    公开(公告)日：2005-05-19

    申请号：US10817777

    申请日：2004-04-02

    申请人： Jui-Lung Chen ,  Yang-Chen Hsu ,  Chien-Jiun Wang

    发明人： Jui-Lung Chen ,  Yang-Chen Hsu ,  Chien-Jiun Wang

    IPC分类号： H01L27/06 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L27/0629

    摘要： A semiconductor programmable device is provided. The semiconductor programmable device comprises a P-type substrate, an N-well, an NMOS capacitor and a PMOS transistor. The N-well is formed in the P-type substrate. The NMOS capacitor is configured on the P-type substrate. The PMOS transistor is configured on the N-well. A source/drain of the PMOS transistor is electrically connected to a gate of the NMOS capacitor. A control voltage is applied to a gate of the PMOS transistor. A programming voltage is applied to the source/drain of the PMOS transistor. The programming voltage is large enough to cause a breakdown of a gate oxide layer of the NMOS capacitor. The gate oxide layer of the NMOS capacitor has a thickness identical to the gate oxide layer of the PMOS transistor.

    摘要翻译： 提供半导体可编程器件。 半导体可编程器件包括P型衬底，N阱，NMOS电容器和PMOS晶体管。 在P型衬底中形成N阱。 NMOS电容器配置在P型基板上。 PMOS晶体管配置在N阱上。 PMOS晶体管的源极/漏极电连接到NMOS电容器的栅极。 控制电压施加到PMOS晶体管的栅极。 对PMOS晶体管的源极/漏极施加编程电压。 编程电压足够大，导致NMOS电容器的栅极氧化层的击穿。 NMOS电容器的栅极氧化层具有与PMOS晶体管的栅氧化层相同的厚度。

    Charging plug
    5.
    发明授权
    Charging plug 有权

    公开(公告)号：US11329421B2

    公开(公告)日：2022-05-10

    申请号：US16928015

    申请日：2020-07-14

    申请人： Jui Lung Chen

    发明人： Jui Lung Chen

    IPC分类号： H01R13/44 ,  H01R13/52 ,  H02J7/00 ,  H01R13/512 ,  B60R16/02

    摘要： A charging plug for high-current charging equipment, the upper end face of main body is provided with an abutting hole corresponding to the socket, and the conducting strips are partially exposed in the abutting hole. A boss extends transversely along the edge of abutting hole in the main body. The charging plug is provided with a protective cover. The protective cover comprises a cover body matching the abutting hole, a collar part fitted over main body and an interconnecting piece connecting the cover body with collar part.

    Memory and storage device utilizing the same
    6.
    发明授权
    Memory and storage device utilizing the same 有权
    使用其的存储和存储设备

    公开(公告)号：US07929328B2

    公开(公告)日：2011-04-19

    申请号：US12484088

    申请日：2009-06-12

    申请人： Jui-Lung Chen

    发明人： Jui-Lung Chen

    IPC分类号： G11C11/40

    CPC分类号： G11C8/08 ,  G11C17/12 ,  G11C2207/005

    摘要： A storage device including a memory and a reading circuit is disclosed. The memory includes a plurality of word lines, a first bit line, a second bit line, a third bit line, and a plurality of cells. The word lines are sequentially disposed in parallel. The first, the second, and the third bit lines are sequentially disposed in parallel and vertical with the word lines. Each cell corresponds to one word line and one bit line. The word line, which corresponds to the cell corresponding to the first bit line, differs from the word line, which corresponds to the cell corresponding to the second bit line. The read circuit is coupled to the memory for reading the data stored in the memory.

    摘要翻译： 公开了一种包括存储器和读取电路的存储装置。 存储器包括多个字线，第一位线，第二位线，第三位线和多个单元。 字线顺序地并列设置。 第一，第二和第三位线与字线平行且垂直地顺序地布置。 每个单元对应一个字线和一个位线。 对应于与第一位线对应的单元的字线与对应于第二位线的单元的字线不同。 读取电路耦合到存储器，用于读取存储在存储器中的数据。

    Static random access memory
    7.
    发明申请
    Static random access memory 有权
    静态随机存取存储器

    公开(公告)号：US20080137398A1

    公开(公告)日：2008-06-12

    申请号：US11636524

    申请日：2006-12-11

    申请人： Jui-Lung Chen ,  Gia-Hua Hsieh ,  Yi-Hsun Chung ,  Chia-Chiuan Chang ,  Yu-Chih Yeh ,  Ho-Hsiang Chen

    发明人： Jui-Lung Chen ,  Gia-Hua Hsieh ,  Yi-Hsun Chung ,  Chia-Chiuan Chang ,  Yu-Chih Yeh ,  Ho-Hsiang Chen

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C11/413

    摘要： A static random access memory comprising a column driver, a row driver, a cell, and a control unit is disclosed. The column driver selects a first word line or a second word line. The row provides data to a first bit line and a second bit line. The data of the first bit line is opposite to that of the second bit line. The control unit controls the voltage of the cell. In normal mode, the voltage of the cell is equal to a second voltage. In stand-by mode, the voltage of the cell exceeds the second voltage.

    摘要翻译： 公开了一种包括列驱动器，行驱动器，单元和控制单元的静态随机存取存储器。 列驱动器选择第一字线或第二字线。 该行将数据提供给第一位线和第二位线。 第一位线的数据与第二位线的数据相反。 控制单元控制电池的电压。 在正常模式下，电池的电压等于第二电压。 在待机模式下，电池的电压超过第二电压。

    Delay lock circuit using bisection algorithm and related method
    8.
    发明授权
    Delay lock circuit using bisection algorithm and related method 有权
    延迟锁电路采用二分法算法及相关方法

    公开(公告)号：US06900678B2

    公开(公告)日：2005-05-31

    申请号：US09682303

    申请日：2001-08-16

    申请人： Jui-Lung Chen ,  Shih-Huang Huang

    发明人： Jui-Lung Chen ,  Shih-Huang Huang

    IPC分类号： H03L7/081 ,  H03L7/10 ,  H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/10

    摘要： A method for performing a delay lock to generate a second clock according to a first clock and to synchronize the second clock with the first clock is provided. The method has correcting processes executed to increase or decrease, by a correction interval, a delay time between corresponding periods of the first clock and the second clock. The correction interval for a subsequent correcting process is substantially half the previous correction interval of the previous correcting process.

    摘要翻译： 提供一种用于执行延迟锁以根据第一时钟产生第二时钟并使第二时钟与第一时钟同步的方法。 该方法具有执行校正处理，以通过校正间隔增加或减少第一时钟和第二时钟的相应周期之间的延迟时间。 用于后续校正处理的校正间隔实际上是先前校正处理的先前校正间隔的一半。

    Poly Fuse Burning System
    10.
    发明申请
    Poly Fuse Burning System 有权
    保险丝燃烧系统

    公开(公告)号：US20120081826A1

    公开(公告)日：2012-04-05

    申请号：US13047567

    申请日：2011-03-14

    申请人： Jui-Lung Chen ,  Tien-Hui Huang ,  Chieh-Yao Chuang

    发明人： Jui-Lung Chen ,  Tien-Hui Huang ,  Chieh-Yao Chuang

    IPC分类号： H02H5/04

    CPC分类号： G11C17/16

    摘要： This invention provides a poly fuse burning system comprising a poly fuse, a controllable power source supplying power for burning the poly fuse, and a monitor circuit monitoring the burning state of the poly fuse, wherein when a targeted burning state is reached, a control signal is output to shut down the controllable power source to stop the burning.

    摘要翻译： 本发明提供一种多熔丝燃烧系统，包括多晶硅熔丝，提供用于燃烧多晶硅熔丝的功率的可控电源，以及监控多晶硅熔丝的燃烧状态的监控电路，其中当达到目标燃烧状态时，控制信号 输出关闭可控电源以停止燃烧。