公开(公告)号：US08913415B2

公开(公告)日：2014-12-16

申请号：US13835308

申请日：2013-03-15

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C17/16 ,  G11C17/06 ,  G11C17/14 ,  H01L43/08 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24

CPC classification number: G11C17/06 ,  G11C17/14 ,  H01L27/224 ,  H01L27/226 ,  H01L27/228 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2445 ,  H01L27/2463 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, or combination thereof.

Abstract translation: 以标准CMOS逻辑工艺制造的结二极管可用作一次性可编程（OTP）器件的程序选择器，例如电熔丝，接触/通孔保险丝，接触/通孔抗熔丝或栅极氧化物击穿反熔丝， OTP器件具有至少一个耦合到存储器单元中的至少一个二极管的OTP元件。 二极管可以由CMOS N阱中的P +和N +有源区域或作为二极管的P和N端子的隔离有源区域构成。 可以通过虚拟MOS栅极，SBL或STI / LOCOS隔离来提供单元中或单元之间的二极管的P +与N +有源区之间的隔离。 OTP元件可以是多晶硅，硅化多晶硅，硅化物，金属，金属合金，局部互连，热隔离有源区，CMOS栅极或其组合。

公开(公告)号：US20140340954A1

公开(公告)日：2014-11-20

申请号：US14231404

申请日：2014-03-31

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C8/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C7/10 ,  G11C8/18 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C17/00 ,  G11C17/146 ,  G11C17/16 ,  G11C29/022 ,  G11C29/027 ,  G11C29/1201 ,  G11C29/46 ,  G11C2216/30

Abstract: A low-pin-count non-volatile (NVM) memory with no more than two control signals that can at least program NVM cells, load data to be programmed into output registers, or read the NVM cells. At least one of the NVM cells has at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector is coupled to a second supply voltage line and having a select signal. At least one of the selected NVM cells can be coupled to at least one output register. No more than two control signals can be used to select the at least one NVM cells in the NVM sequentially for programming the data into the at least one NVM cells or loading data into the at least one output registers controlled by the pulse of the first signal and voltage level and/or timing of the second signal. Programming into the NVM cells, or loading data into output registers, can be determined by the voltage levels of the first to the second supply voltage lines. Reading at least one of the NVM cells can be activated by a third signal or by detecting ramping of the first or the second supply voltage line.

Abstract translation: 具有不超过两个控制信号的低引脚数非易失性（NVM）存储器，可以至少编程NVM单元，将要编程的数据加载到输出寄存器中，或读取NVM单元。 至少一个NVM单元具有耦合到至少一个选择器和第一电源电压线的至少一个NVM元件。 选择器耦合到第二电源电压线并且具有选择信号。 所选择的NVM单元中的至少一个可以耦合到至少一个输出寄存器。 可以使用不超过两个控制信号来选择NVM中的至少一个NVM单元以将数据编程到至少一个NVM单元中，或者将数据加载到由第一信号的脉冲控制的至少一个输出寄存器中 和第二信号的电压电平和/或定时。 可以通过第一至第二电源电压线的电压电平来确定对NVM单元的编程或将数据加载到输出寄存器中。 读取至少一个NVM单元可以被第三信号激活或通过检测第一或第二电源电压线的斜坡。

公开(公告)号：US08854859B2

公开(公告)日：2014-10-07

申请号：US13026840

申请日：2011-02-14

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C11/00 ,  G11C13/00 ,  G11C17/16 ,  G11C11/16 ,  H01L29/78

CPC classification number: H01L27/2436 ,  G11C8/14 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/785 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a voltage or a current between a reversible resistive element and the N terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations.

Abstract translation: 以标准CMOS逻辑处理器制造的结二极管可用作可逆电阻器件（如PCM，RRAM，CBRAM或其他存储器单元）的程序选择器。 可逆电阻器件具有耦合到二极管的可逆电阻元件。 二极管可以由N阱上的P +和N +有源区构成，作为二极管的P和N端。 通过在可逆电阻元件和二极管的N端之间施加电压或电流，可逆电阻器件可以以可逆的方式基于幅度，持续时间，电压限制或电流限制被编程到不同的状态。 通过使用虚拟MOS栅极，SBL或STI / LOCOS隔离，二极管的P +有源区可以与N阱中的N +有源区隔离。

公开(公告)号：US08804398B2

公开(公告)日：2014-08-12

申请号：US13026852

申请日：2011-02-14

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C11/00

CPC classification number: G11C17/06 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/785 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive memory cells that can be programmed based on magnitude, duration, voltage-limit, or current-limit of a supply voltage or current. These cells are PCM, RRAM, CBRAM, or other memory cells that have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. The memory cells can be used to construct a two-dimensional memory array with the N terminals of the diodes in a row connected as a wordline and the reversible resistive elements in a column connected as a bitline. By applying a voltage or a current to a selected bitline and to a selected wordline to turn on the diode, a selected cell can be programmed into different states reversibly based on magnitude, duration, voltage-limit, or current-limit. The data in the reversible resistive memory can also be read by turning on a selected wordline to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistive global wordlines through conductive contact(s) or via(s).

Abstract translation: 以标准CMOS逻辑处理器制造的结二极管可用作可逆电阻存储器单元的程序选择器，可根据电源电压或电流的幅度，持续时间，电压限制或电流限制进行编程。 这些单元是具有耦合到二极管的可逆电阻元件的PCM，RRAM，CBRAM或其它存储单元。 二极管可以由N阱上的P +和N +有源区构成，作为二极管的P和N端。 存储单元可以用于构造二维存储器阵列，其中二极管的N个端子作为字线连接，并且作为位线连接的列中的可逆电阻元件。 通过将电压或电流施加到所选择的位线和选定的字线以打开二极管，所选择的单元可以根据幅度，持续时间，电压限制或限流可逆地编程为不同的状态。 可逆电阻存储器中的数据也可以通过打开所选择的字线来读取，以将选定的位线耦合到读出放大器。 字线可以具有通过导电接点或通孔耦合到低电阻全局字线的高电阻本地字线。

公开(公告)号：US08760916B2

公开(公告)日：2014-06-24

申请号：US13026835

申请日：2011-02-14

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C11/15

CPC classification number: H01L27/2436 ,  G11C8/14 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/785 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

Abstract: At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for memory cells that can be programmed based on direction of current flow. These cells are MRAM, RRAM, CBRAM, or other memory cells that have a programmable resistive element coupled to a P terminal of a first diode and to an N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. The memory cells can be used to construct a two-dimensional memory array with the N terminals of the first diodes and the P terminals of the second diodes in a row connected as wordline(s) and the resistive elements in a column connected as a bitline. By applying a high voltage to a selected bitline and a low voltage to a selected wordline to turn on the first diode while disabling the second diode, a selected cell can be programmed into one state. Similarly, by applying a low voltage to a selected bitline and a high voltage to a selected wordline to turn on the second diode while disabling the first diode, a selected cell can be programmed into another state. The data in the resistive memory cell can also be read by turning on a selected wordline to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s).

Abstract translation: 在标准CMOS逻辑工艺中制造的至少一个结二极管可用作可根据电流方向编程的存储器单元的程序选择器。 这些单元是具有耦合到第一二极管的P端子和第二二极管的N端子的可编程电阻元件的MRAM，RRAM，CBRAM或其它存储器单元。 二极管可以由N阱上的P +和N +有源区域构成，作为二极管的P和N端子。 存储单元可用于构建二维存储器阵列，其中第一二极管的N端和第二二极管的P端作为字线连接，并且作为位线连接的列中的电阻元件作为位线 。 通过将高电压施加到所选择的位线和低电压到所选择的字线以在禁用第二二极管的同时接通第一二极管，所选择的单元可以被编程为一个状态。 类似地，通过将​​低电压施加到所选择的位线和高电压到所选择的字线以在禁用第一二极管的同时接通第二二极管，所选择的单元可以被编程到另一状态。 也可以通过打开所选择的字线来读取电阻存储器单元中的数据，以将选定的位线耦合到读出放大器。 字线可以具有通过导电接触或通孔耦合到低电阻率全局字线的高电阻率局部字线。

公开(公告)号：US08760904B2

公开(公告)日：2014-06-24

申请号：US13026771

申请日：2011-02-14

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C17/00 ,  H01L23/52

CPC classification number: H01L27/2436 ,  G11C8/14 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/785 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. The OTP device has an OTP element coupled to the diode. The OTP device can be used to construct a two-dimensional OTP memory with the N terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline.

Abstract translation: 以标准CMOS逻辑工艺制造的结二极管可用作一次性可编程（OTP）器件的程序选择器，例如电熔丝，接触/通孔保险丝，接触/通孔抗熔丝或栅极氧化物击穿反熔丝， 二极管可以由N阱上的P +和N +有源区域构成，作为二极管的P和N端子。 OTP器件具有耦合到二极管的OTP元件。 OTP设备可以用于构建二维OTP存储器，其中连接作为字线的二极管的N个端子和作为位线连接的列中的OTP元件。

公开(公告)号：US20130308366A1

公开(公告)日：2013-11-21

申请号：US13954831

申请日：2013-07-30

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C17/16

CPC classification number: H01L27/2436 ,  G11C8/14 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/785 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal are connected in a single rectangular contact.

Abstract translation: 以标准CMOS逻辑工艺制造的结二极管可用作一次性可编程（OTP）器件的程序选择器，例如电熔丝，接触/通孔保险丝，接触/通孔抗熔丝或栅极氧化物击穿反熔丝， OTP器件具有耦合到存储器单元中的二极管的OTP元件。 二极管可以由N阱上的P +和N +有源区构成，作为二极管的P和N端。 通过将高电压施加到二极管的P端子并将二极管的N端子切换到低电压适当的持续时间，与程序选择器串联的OTP元件的电流可能改变电阻状态。 通过使用虚拟MOS栅极，SBL或STI / LOCOS隔离，二极管的P +有源区可以与N阱中的N +有源区隔离。 如果电阻元件是基于CMOS栅极材料的互连熔丝，则电阻元件可通过邻接触点耦合到P +有源区，使得元件，有源区和金属以单个矩形接触连接。

公开(公告)号：US08559208B2

公开(公告)日：2013-10-15

申请号：US13026704

申请日：2011-02-14

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C11/00

CPC classification number: H01L27/2436 ,  G11C8/14 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/785 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

Abstract: Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices such as PCRAM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. By applying a voltage or a current between a reversible resistive element and the N-terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. On the polysilicon diode, the spacing and doping level of a gap between the P- and N-implants can be controlled for different breakdown voltages and leakage currents. The Silicide Block Layer (SBL) can be used to block silicide formation on the top of polysilicon to prevent shorting.

Abstract translation: 以标准CMOS逻辑工艺制造的多晶硅二极管可用作可逆电阻器件（如PCRAM，RRAM，CBRAM或其他存储器单元）的程序选择器。 可逆电阻器件具有耦合到二极管的可逆电阻元件。 二极管可以由多晶硅上的P + / N +种植体构成，作为程序选择器。 通过在可逆电阻元件和二极管的N端之间施加电压或电流，可逆电阻器件可以以可逆的方式基于幅度，持续时间，电压限制或电流限制被编程到不同的状态。 在多晶硅二极管上，可以对不同的击穿电压和漏电流来控制P型和N型注入之间的间隙和掺杂水平。 硅化物阻挡层（SBL）可用于阻挡多晶硅顶部的硅化物形成以防止短路。

公开(公告)号：US08514606B2

公开(公告)日：2013-08-20

申请号：US13026752

申请日：2011-02-14

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C17/00

CPC classification number: H01L27/2436 ,  G11C8/14 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/785 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal are connected in a single rectangular contact.

Abstract translation: 以标准CMOS逻辑工艺制造的结二极管可用作一次性可编程（OTP）器件的程序选择器，例如电熔丝，接触/通孔保险丝，接触/通孔抗熔丝或栅极氧化物击穿反熔丝， OTP器件具有耦合到存储器单元中的二极管的OTP元件。 二极管可以由N阱上的P +和N +有源区构成，作为二极管的P和N端。 通过将高电压施加到二极管的P端子并将二极管的N端子切换到低电压适当的持续时间，与程序选择器串联的OTP元件的电流可能改变电阻状态。 通过使用虚拟MOS栅极，SBL或STI / LOCOS隔离，二极管的P +有源区可以与N阱中的N +有源区隔离。 如果电阻元件是基于CMOS栅极材料的互连熔丝，则电阻元件可通过邻接触点耦合到P +有源区，使得元件，有源区和金属以单个矩形接触连接。

公开(公告)号：US20120044746A1

公开(公告)日：2012-02-23

申请号：US13026725

申请日：2011-02-14

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C11/36 ,  H01L45/00 ,  G11C11/02

CPC classification number: H01L27/2436 ,  G11C8/14 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/785 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

Abstract: Junction diodes fabricated in standard CMOS logic technologies can be used as program selectors for a programmable resistive device, such as electrical fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCM, CBRAM, or RRAM. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for proper duration of time, a current flows through a resistive element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal can be connected in a single rectangular contact.

Abstract translation: 以标准CMOS逻辑技术制造的结二极管可用作可编程电阻器件的编程选择器，例如电熔丝，触点/通路保险丝，反熔丝或出现的非易失性存储器，如MRAM，PCM，CBRAM或RRAM。 二极管可以由N阱上的P +和N +有源区构成，作为二极管的P和N端。 通过向二极管的P端子施加高电压并将二极管的N端子切换到低电压适当的持续时间，与程序选择器串联的电阻元件的电流可能改变电阻状态。 二极管的P +有源区可以通过使用虚拟MOS栅极，SBL或STI隔离来与N阱中的N +有源区隔离。 如果电阻元件是基于CMOS栅极材料的互连熔丝，则电阻元件可以通过邻接触点耦合到P +有源区，使得元件，有源区和金属可以以单个矩形接触连接。