公开(公告)号：US12066941B2

公开(公告)日：2024-08-20

申请号：US17961146

申请日：2022-10-06

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook ,  Leigang Kou

IPC: G06F12/08 ,  G01N29/24 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0846 ,  G06F12/0891 ,  G06F12/123 ,  H01S5/042 ,  H01S5/06 ,  H01S5/10

CPC classification number: G06F12/0811 ,  G01N29/2418 ,  G06F12/0813 ,  G06F12/0846 ,  G06F12/0891 ,  G06F12/123 ,  H01S5/0427 ,  H01S5/0612 ,  H01S5/1042 ,  H01S5/1096 ,  G06F2212/1021

Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.

公开(公告)号：US20240104024A1

公开(公告)日：2024-03-28

申请号：US18475310

申请日：2023-09-27

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Andrew Waterman

IPC: G06F12/1009

CPC classification number: G06F12/1009

Abstract: Systems and methods are disclosed for atomic memory operations for address translation. For example, an integrated circuit (e.g., a processor) for executing instructions includes a memory system including random access memory; a bus connected to the memory system; and an atomic memory operation circuitry configured to receive a request from the bus to access an entry in a page table stored in the memory system, wherein the request includes an indication of whether an instruction that references an address being translated using the entry is a store instruction; access the entry in the page table; responsive to the indication indicating that the instruction is a store instruction, set a dirty bit of the entry in the page table; and transmit contents of the entry on the bus in response to the request.

公开(公告)号：US11687455B2

公开(公告)日：2023-06-27

申请号：US17961137

申请日：2022-10-06

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/128

CPC classification number: G06F12/0804 ,  G06F12/128 ,  G06F2212/1008

Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.

公开(公告)号：US11620229B2

公开(公告)日：2023-04-04

申请号：US16797476

申请日：2020-02-21

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Josh Smith

IPC: G06F12/0888 ,  G06F12/0862

Abstract: Described is a data cache with prediction hints for a cache hit. The data cache includes a plurality of cache lines, where a cache line includes a data field, a tag field, and a prediction hint field. The prediction hint field is configured to store a prediction hint which directs alternate behavior for a cache hit against the cache line. The prediction hint field is integrated with the tag field or is integrated with a way predictor field.

公开(公告)号：US11023375B1

公开(公告)日：2021-06-01

申请号：US16797478

申请日：2020-02-21

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook

IPC: G06F12/0804 ,  G06F12/128

Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.

公开(公告)号：US20240184581A1

公开(公告)日：2024-06-06

申请号：US18497170

申请日：2023-10-30

Applicant: SiFive, Inc.

Inventor： Benoy Alexander ,  John Ingalls ,  Binayak Tiwari

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30047 ,  G06F9/3816 ,  G06F9/3836

Abstract: Described herein is a bit pattern matching hardware prefetcher which captures complex repeating patterns, allows out-of-order (OOO) training, and allows OOO confirmations. The prefetcher includes a plurality of prefetch engines. Each prefetch engine is associated with a zone, each zone has a plurality of subzones, and each subzone has a plurality of cache lines. The prefetcher includes an access map for each subzone. Each bit position represents a cache line in the plurality of cache lines. The prefetcher determines whether a demand request matches one of the plurality of prefetch engines, updates, with respect to the demand request, a bit position in an access map for a subzone in a matching prefetch engine, determines a pattern from an access map for a subzone when a defined number of demand requests have been matched to the subzone; and generates a prefetch request based on at least the determined pattern.

公开(公告)号：US20230333861A1

公开(公告)日：2023-10-19

申请号：US18191074

申请日：2023-03-28

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Paul Walmsley ,  John Ingalls

IPC: G06F9/445

CPC classification number: G06F9/44505

Abstract: A first operating system process may be identified. The first operating system process may have instructions configured to be executed by a processor core. A first set of parameters may be determined based on an attribute of the first operating system process. For example, the first set of parameters may be determined based on an address space identifier, an address space stored in a page table base register, a virtual machine identifier, or a combination thereof. A component of the processor core may be configured using the first set of parameters. For example, one or more components, such as a branch predictor, a prefetcher, a dispatch unit, a vector unit, a clock controller, and the like, may be configured using the first set of parameters.

公开(公告)号：US20230195647A1

公开(公告)日：2023-06-22

申请号：US18086635

申请日：2022-12-21

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Andrew Waterman

IPC: G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/1032

Abstract: Systems and methods are disclosed for logging guest physical address for memory access faults. For example, a method for logging guest physical address includes receiving a first address translation request from a processor pipeline at a translation lookaside buffer for a first guest virtual address; identifying a hit with a fault condition corresponding to the first guest virtual address; responsive to the fault condition, invoking a single-stage page table walk with the first guest virtual address to obtain a first guest physical address; and storing the first guest physical address with the first guest virtual address in a data store, wherein the data store is separate from an entry in the translation lookaside buffer that includes a tag that includes the first guest virtual address and data that includes a physical address.

公开(公告)号：US11467962B2

公开(公告)日：2022-10-11

申请号：US17009876

申请日：2020-09-02

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook ,  Leigang Kou

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0846 ,  G06F12/0891 ,  G06F12/123

Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.

公开(公告)号：US20220066936A1

公开(公告)日：2022-03-03

申请号：US17009876

申请日：2020-09-02

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook ,  Leigang Kou

IPC: G06F12/0811 ,  G06F12/0891 ,  G06F12/0846 ,  G06F12/0813 ,  G06F12/123

Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.