-
公开(公告)号：US10511315B1
公开(公告)日：2019-12-17
申请号：US16138080
申请日：2018-09-21
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
Abstract: An apparatus includes a control circuit configured to generate a frequency divider control signal approximating a fractional divide ratio. The apparatus includes a frequency divider configured to generate an output clock signal based on an input clock signal and an adjusted frequency divider control signal. The output clock signal is a frequency-divided version of the input clock signal. The apparatus includes a measurement circuit configured to provide digital time information corresponding to an edge of the output clock signal. The apparatus includes an adaptive adjustment circuit configured to generate the adjusted frequency divider control signal based on the frequency divider control signal and the digital time information.
-
公开(公告)号：US20190094302A1
公开(公告)日：2019-03-28
申请号：US15713178
申请日：2017-09-22
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
IPC: G01R31/3185 , G05F1/10 , G01R31/319
Abstract: During scan testing a voltage regulator is programmed to supply a first voltage to logic under test during a shift portion of the scan test, a second voltage during a first portion of a capture portion of the scan test and at least a third voltage during a second portion of the capture portion of the scan test. The availability of a programmable voltage regulator during shift and capture portions of scan testing allows a less stressful voltage to be used during a shift portion of the scan test to reduce shift failures and allows various voltages to be used during capture portions of the scan testing as a surrogate for testing at different temperatures and to provide more flexibility in testing margins.
-
13.发明申请公开(公告)号：US20180175871A1
公开(公告)日：2018-06-21
申请号：US15385311
申请日：2016-12-20
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
IPC: H03L7/197
CPC classification number: H03L7/1974 , H03L7/081 , H03L7/1976
Abstract: An interpolative divider includes a look ahead sigma delta modulator circuit to generate divide values according to a divide ratio. A plurality of M storage elements are coupled to the sigma delta modulator to store the divide values, M being at least 2. A selector circuit selects the respective divide values and supplies the divide values to a portion of an interpolative divider circuit, the portion including a divider and a phase interpolator. The interpolative divider generates an output clock signal having a first clock period that may be determined by the first and second divide values. The M storage elements are loaded by a clock signal that is slower than the output clock signal by at least half.
-
公开(公告)号：US20210328758A1
公开(公告)日：2021-10-21
申请号：US16849036
申请日：2020-04-15
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
Abstract: A line card in a network box receives a SyncE clock signal and an input SYNC signal. A phase-lock loop (PLL) in the line card receives the SyncE clock signal as a reference clock signal and generates an output SyncE clock signal. The line card regenerates a SYSCLK signal using a digitally controlled oscillator that receives a timing signal from the SyncE PLL and receives a control signal from control logic on the line card. The frequency and phase information contained in the SYNC signal is utilized to control the DCO. The SYSCLK signal is divided to generate an output SYNC signal. The control logic uses the time difference between the input SYNC signal and a SYNC feedback signal to control the DCO to provide a zero delay SYNC output signal. The output SYNC signal and the SYSCLK signal control a time of day counter in the line card.
-
Patent Agency Ranking
公开(公告)号：US11061432B2
公开(公告)日：2021-07-13
申请号：US16693559
申请日：2019-11-25
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
Abstract: A data handoff controller includes a counter coupled to supply a count value indicative of a skew between a first clock signal and a second clock signal. The first and second clock signal have a fundamental beat frequency. A greatest common factor circuit is used to determine the fundamental beat frequency and the second is reset based on the beat frequency. A sampling circuit samples first clock domain data with the second clock signal. The sampling circuit is controlled to sample, at least in part, based on the count value. The count value can be used to impose a blackout window in which data is not sampled to avoid sampling data around data transitions of the first clock domain data. The count value can also be used to select an edge of the second clock signal to use for sampling the first clock domain data to ensure first clock domain data is not sampled during data transitions.
-
公开(公告)号：US10908635B1
公开(公告)日：2021-02-02
申请号：US16726481
申请日：2019-12-24
Applicant: Silicon Laboratories Inc.
Inventor： Harihara Subramanian Ranganathan , Vivek Sarda
Abstract: A method for generating a clock signal includes selecting a primary reference clock signal or a secondary reference clock signal as a reference clock signal for a phase-locked loop configured to generate an output clock signal. The method includes generating an indication of whether a failure of the reference clock signal has occurred by monitoring the secondary reference clock signal and a plurality of additional clock signals using the reference clock signal. The failure is determined based on whether a gross failure of the reference clock signal has occurred and if the gross failure has not occurred, further based on whether a quality failure of the reference clock signal has occurred.
-
17.发明申请公开(公告)号：US20200285265A1
公开(公告)日：2020-09-10
申请号：US16295255
申请日：2019-03-07
Applicant: Silicon Laboratories Inc.
Inventor： Harihara Subramanian Ranganathan , Vivek Sarda
Abstract: In order to reduce errors in the transfer of time from one clock domain to another clock domain, a first free running counter is incremented using a first clock signal. A free running second counter is incremented using a second clock signal, the second clock signal being asynchronous to the first clock signal. The first counter is sampled at a selected time based on a predetermined phase relationship between the first clock signal and the second clock signal to generate a sampled first counter value. The second counter is corrected based on the sampled first counter value.
-
公开(公告)号：US10075173B2
公开(公告)日：2018-09-11
申请号：US15358898
申请日：2016-11-22
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
CPC classification number: H03L7/093 , H03L7/0802 , H03L7/081 , H03L7/0816 , H03L7/0992 , H03L7/10
Abstract: A phase-locked loop uses an edge detect circuit to detect an edge of an input clock signal. The detected edge is used to digitally align an initial edge of the feedback signal with the input clock signal to the PLL so that the feedback signal is substantially aligned with the input clock signal. The edge alignment of the feedback signal may be performed at startup or in response to loss of lock/input clock switching. By aligning the feedback signal the input clock signal based on the edge detect, faster lock occurs.
-
公开(公告)号：US20180145696A1
公开(公告)日：2018-05-24
申请号：US15358898
申请日：2016-11-22
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
CPC classification number: H03L7/093 , G01R23/02 , H03L7/0802 , H03L7/081 , H03L7/0816 , H03L7/0992 , H03L7/10
Abstract: A phase-locked loop uses an edge detect circuit to detect an edge of an input clock signal. The detected edge is used to digitally align an initial edge of the feedback signal with the input clock signal to the PLL so that the feedback signal is substantially aligned with the input clock signal. The edge alignment of the feedback signal may be performed at startup or in response to loss of lock/input clock switching. By aligning the feedback signal the input clock signal based on the edge detect, faster lock occurs.
-
-
-
-
-
-
-
-
Search Results
19
records
(took 0.014 seconds)
