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    Successive Approximation Register Analog-to-Digital Converter With Single-Ended Measurement
    13.
    发明申请
    Successive Approximation Register Analog-to-Digital Converter With Single-Ended Measurement 有权
    具有单端测量功能的逐次逼近寄存器模数转换器

    公开(公告)号：US20150091746A1

    公开(公告)日：2015-04-02

    申请号：US14511088

    申请日：2014-10-09

    Applicant: Silicon Laboratories Inc.

    Inventor： Xiaodong Wang

    IPC: H03M1/46 ,  H03M1/80 ,  H03M1/66

    CPC classification number: H03M1/1245 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/466 ,  H03M1/804

    Abstract: A circuit may include a comparator having a first input, a second input, and an output. The circuit further may further include a successive approximation register (SAR) circuit coupled to the output of the comparator, the first input, and the second input. The SAR circuit may be configured to program one or more capacitors to selectively bias the first input to provide a single-ended measurement of a voltage at the second input.

    Abstract translation: 电路可以包括具有第一输入，第二输入和输出的比较器。 电路还可以包括耦合到比较器的输出，第一输入和第二输入的逐次逼近寄存器（SAR）电路。 SAR电路可以被配置为对一个或多个电容器进行编程，以选择性地偏置第一输入以提供第二输入端的电压的单端测量。

    Incremental analog to digital converter with efficient residue conversion
    15.
    发明授权
    Incremental analog to digital converter with efficient residue conversion 有权

    公开(公告)号：US09866238B1

    公开(公告)日：2018-01-09

    申请号：US15499540

    申请日：2017-04-27

    Applicant: SILICON LABORATORIES INC.

    Inventor： Axel Thomsen ,  Xiaodong Wang

    IPC: H03M1/12 ,  H03M3/00

    CPC classification number: H03M3/462 ,  H03M3/422 ,  H03M3/452

    Abstract: An incremental analog to digital converter for digitizing an analog voltage including an Mth order delta sigma modulator, an Mth order digital decimation filter, a controller, and a digital combiner. The controller operates the modulator to convert the analog voltage into multiple digital samples, and operates the digital decimation filter to convert the digital samples into a preliminary digital output value. The controller further operates the delta sigma modulator during a residue phase for M clock cycles in which the modulator provides a digital residue value. The digital combiner combines the preliminary digital output value with the digital residue value to provide an initial digital output value. For an Mth order system, only M additional cycles are needed to extract the residual value to increase the resolution of the digital output by an amount based on the resolution of a modulator quantizer.

    Dual-path comparator and method
    17.
    发明授权
    Dual-path comparator and method 有权
    双路比较器和方法

    公开(公告)号：US09041584B2

    公开(公告)日：2015-05-26

    申请号：US14016948

    申请日：2013-09-03

    Applicant: Silicon Laboratories Inc.

    Inventor： Xiaodong Wang ,  Shouli Yan ,  Axel Thomsen

    IPC: H03M1/12 ,  H03M1/42 ,  H03M1/38 ,  H03M1/40

    CPC classification number: H03M1/42 ,  H03M1/0692 ,  H03M1/188 ,  H03M1/38 ,  H03M1/403 ,  H03M1/466

    Abstract: A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value.

    Abstract translation: 一种方法包括在比较器的第一和第二输入处接收差分电压信号，并且在转换阶段期间选​​择性地将差分电压信号提供给比较器的第一转换路径和第二转换路径中的一个，以确定对应于 差分电压信号。 第一和第二转换路径分别包括第一和第二多个增益级。 该方法还包括将所选择的第一转换路径和第二转换路径中的一个耦合到输出以提供数字值。

    APPARATUS FOR MIXED SIGNAL INTERFACE ACQUISITION CIRCUITRY AND ASSOCIATED METHODS
    18.
    发明申请
    APPARATUS FOR MIXED SIGNAL INTERFACE ACQUISITION CIRCUITRY AND ASSOCIATED METHODS 有权
    混合信号接口电路和相关方法的装置

    公开(公告)号：US20140002133A1

    公开(公告)日：2014-01-02

    申请号：US13799159

    申请日：2013-03-13

    Applicant: SILICON LABORATORIES INC.

    Inventor： Clayton Daigle ,  Jinwen Xiao ,  Axel Thomsen ,  Subrata Roy ,  Xiaodong Wang

    IPC: H03K19/0175

    CPC classification number: H03K19/017509

    Abstract: An integrated circuit (IC) includes a plurality of pads adapted to communicate signals with a circuit external to the IC, and a first mixed signal interface block coupled to a first pad in the plurality of pads, where the first mixed signal interface block is adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal. The IC further includes a second mixed signal interface block coupled to a second pad in the plurality of pads, where the second mixed signal interface block is adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC. The second mixed signal interface block is further adapted to generate, in response to the second trigger signal, a first output signal based on the first input signal and to provide the first output signal to a digital core of the IC in a second mode of operation of the IC, where the power consumption of the IC is lower in the first mode of operation than in the second mode of operation.

    Abstract translation: 集成电路（IC）包括适于与IC外部的电路传送信号的多个焊盘以及耦合到多个焊盘中的第一焊盘的第一混合信号接口块，其中第一混合信号接口块被适配 以从IC外部的电路接收第一触发信号并提供第二触发信号。 IC还包括耦合到多个焊盘中的第二焊盘的第二混合信号接口块，其中第二混合信号接口块适于以第一模式的第一模式接收并跟踪来自IC外部的电路的第一输入信号 IC的运作。 第二混合信号接口块还适于响应于第二触发信号而产生基于第一输入信号的第一输出信号，并且在第二操作模式中将第一输出信号提供给IC的数字核心 的IC，其中IC的功耗在第一操作模式中比在第二操作模式中更低。

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