公开(公告)号：US20200349422A1

公开(公告)日：2020-11-05

申请号：US16449205

申请日：2019-06-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stephen Trinh ,  Thuan Vu ,  Stanley Hong ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06N3/063 ,  G11C16/08

Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.

公开(公告)号：US20200242460A1

公开(公告)日：2020-07-30

申请号：US16360733

申请日：2019-03-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly

IPC: G06N3/063 ,  G06N3/08 ,  G11C16/04 ,  G11C16/10

Abstract: Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.

公开(公告)号：US20200019849A1

公开(公告)日：2020-01-16

申请号：US16151259

申请日：2018-10-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Thuan Vu ,  Anh Ly ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/063 ,  G06F3/06 ,  G06F11/16

Abstract: Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.

公开(公告)号：US20250068861A1

公开(公告)日：2025-02-27

申请号：US18385344

申请日：2023-10-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stephen Trinh ,  Hoa Vu ,  Stanley Hong ,  Thuan Vu

IPC: G06J1/00

Abstract: Numerous examples are disclosed of input blocks for an array of non-volatile memory cells and associated methods. In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an input block comprising a plurality of row circuits and a global digital-to-analog converter generator to generate 2m different analog voltages, where m is an integer; wherein the row circuits in the plurality of row circuits respectively apply one of the 2m different analog voltages to an associated row in the array.

公开(公告)号：US12176039B2

公开(公告)日：2024-12-24

申请号：US18140103

申请日：2023-04-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Stephen Trinh ,  Thuan Vu ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/10 ,  G06N3/065 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34

Abstract: In one example, a method comprises determining a program resolution current value; and setting levels for a programming operation of a plurality of non-volatile memory cells in a neural network array such that a delta current between levels of each pair of adjacent cells in the plurality is a multiple of the program resolution current value.

公开(公告)号：US20240312517A1

公开(公告)日：2024-09-19

申请号：US18419079

申请日：2024-01-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/54 ,  G06N3/065 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C11/54 ,  G06N3/065 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C2216/04

Abstract: In one example, a method comprises erasing at the same time a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal, by turning on an erase gate enable transistor coupled to erase gate terminals of the word of non-volatile memory cells.

公开(公告)号：US20240079064A1

公开(公告)日：2024-03-07

申请号：US18139908

申请日：2023-04-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Stephen Trinh ,  Thuan Vu ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/10 ,  G06N3/065 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C16/10 ,  G06N3/065 ,  G11C11/5628 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/3459

Abstract: In one example, a system comprises a neural network array of non-volatile memory cells arranged in rows and columns; and a logical cell comprising a first plurality of non-volatile memory cells in a first row of the array and a second plurality of non-volatile memory cells in a second row adjacent to the first row; wherein the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells are configured as one or more coarse cells and one or more fine cells.

公开(公告)号：US11586898B2

公开(公告)日：2023-02-21

申请号：US16360733

申请日：2019-03-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly

IPC: G06N3/063 ,  G06N3/08 ,  G11C16/04 ,  G11C16/10 ,  G06F12/0811 ,  G11C11/4063 ,  G11C11/54

Abstract: Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.

公开(公告)号：US11568229B2

公开(公告)日：2023-01-31

申请号：US16151259

申请日：2018-10-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Thuan Vu ,  Anh Ly ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/06 ,  G06F3/06 ,  G06F11/16 ,  G06N3/063

Abstract: Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.

公开(公告)号：US20230018166A1

公开(公告)日：2023-01-19

申请号：US17853315

申请日：2022-06-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Han Tran ,  Kha Nguyen ,  Hien Pham

IPC: G11C11/56 ,  G11C11/16 ,  G06N3/06 ,  G11C11/4074 ,  G06F17/16

Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.