公开(公告)号：US11018147B1

公开(公告)日：2021-05-25

申请号：US16781798

申请日：2020-02-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Elizabeth Cuevas ,  Parviz Ghazavi ,  Bernard Bertello ,  Gilles Festes ,  Catherine Decobert ,  Yuri Tkachev ,  Bruno Villard ,  Nhan Do

IPC: H01L21/00 ,  H01L27/11534 ,  H01L21/28 ,  H01L21/311 ,  H01L21/02 ,  H01L29/423 ,  H01L29/08 ,  H01L21/027 ,  H01L27/11521 ,  H01L29/788

Abstract: A method of forming a memory device includes forming a floating gate on a memory cell area of a semiconductor substrate, having an upper surface terminating in an edge. An oxide layer is formed having first and second portions extending along the logic and memory cell regions of the substrate surface, respectively, and a third portion extending along the floating gate edge. A non-conformal layer is formed having a first, second and third portions covering the oxide layer first, second and third portions, respectively. An etch removes the non-conformal layer third portion, and thins but does not entirely remove the non-conformal layer first and second portions. An etch reduces the thickness of the oxide layer third portion. After removing the non-conformal layer first and second portions, a control gate is formed on the oxide layer second portion and a logic gate is formed on the oxide layer first portion.

公开(公告)号：US10818680B2

公开(公告)日：2020-10-27

申请号：US16578104

申请日：2019-09-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11531 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/788

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

公开(公告)号：US20200176578A1

公开(公告)日：2020-06-04

申请号：US16208288

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L27/11521 ,  H01L29/66 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L29/788

Abstract: A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.

公开(公告)号：US11362218B2

公开(公告)日：2022-06-14

申请号：US16910022

申请日：2020-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Elizabeth Cuevas ,  Yuri Tkachev ,  Parviz Ghazavi ,  Bernard Bertello ,  Gilles Festes ,  Bruno Villard ,  Catherine Decobert ,  Nhan Do ,  Jean Francois Thiery

IPC: H01L27/11517 ,  H01L27/11531 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11543 ,  H01L27/11551 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11534

Abstract: A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

公开(公告)号：US20210399127A1

公开(公告)日：2021-12-23

申请号：US16910022

申请日：2020-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Elizabeth Cuevas ,  Yuri Tkachev ,  Parviz Ghazavi ,  Bernard Bertello ,  Gilles Festes ,  Bruno Villard ,  Catherine Decobert ,  Nhan Do ,  Jean Francois Thiery

IPC: H01L29/788 ,  H01L29/66 ,  H01L27/11517

Abstract: A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

公开(公告)号：US20210193671A1

公开(公告)日：2021-06-24

申请号：US16724010

申请日：2019-12-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L27/11517 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/78

Abstract: A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

公开(公告)号：US10998325B2

公开(公告)日：2021-05-04

申请号：US16208297

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Catherine Decobert ,  Hieu Van Tran ,  Nhan Do

IPC: G11C16/16 ,  H01L27/11521 ,  G11C16/26 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

Abstract: A memory device that includes source and drain regions formed in a semiconductor substrate, with a first channel region of the substrate extending there between. A floating gate is disposed over and insulated from the channel region, wherein the conductivity of the channel region is solely controlled by the floating gate. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the source region, wherein the erase gate includes a notch that faces and is insulated from an edge of the floating gate. Logic devices are formed on the same substrate. Each logic device has source and drain regions with a channel region extending there between, and a logic gate disposed over and controlling the logic device's channel region.

公开(公告)号：US10937794B2

公开(公告)日：2021-03-02

申请号：US16208150

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11521 ,  H01L21/28 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A memory device having plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin and a logic device formed on a second fin. The memory cell includes source and drain regions in the first fin with a channel region therebetween, a polysilicon floating gate extending along a first portion of the channel region including the side and top surfaces of the first fin, a metal select gate extending along a second portion of the channel region including the side and top surfaces of the first fin, a polysilicon control gate extending along the floating gate, and a polysilicon erase gate extending along the source region. The logic device includes source and drain regions in the second fin with a second channel region therebetween, and a metal logic gate extending along the second channel region including the side and top surfaces of the second fin.

公开(公告)号：US10727240B2

公开(公告)日：2020-07-28

申请号：US16028244

申请日：2018-07-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L27/1156 ,  H01L27/11524 ,  H01L21/266 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first of the fins, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second of the fins has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.

公开(公告)号：US10468428B1

公开(公告)日：2019-11-05

申请号：US15957615

申请日：2018-04-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.