公开(公告)号：US20230253331A1

公开(公告)日：2023-08-10

申请号：US17897523

申请日：2022-08-29

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yi-Min Fu ,  Chi-Ching Ho ,  Chao-Chiang Pu ,  Yu-Po Wang

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L23/5385 ,  H01L23/5386 ,  H01L21/565 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/3128 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/182 ,  H01L2924/3511 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/107

Abstract: An electronic package is provided, in which an electronic module and at least one support member are disposed on a substrate structure having a circuit layer, such that the stress on the substrate structure is dispersed through the at least one support member to eliminate the problem of stress concentration and prevent the substrate structure from warping.

公开(公告)号：US20230154865A1

公开(公告)日：2023-05-18

申请号：US17572001

申请日：2022-01-10

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chao-Chiang Pu ,  Chi-Ching Ho ,  Yi-Min Fu ,  Yu-Po Wang ,  Po-Yuan Su

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L23/367 ,  H01L23/3107 ,  H01L21/4882 ,  H01L23/585

Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.

公开(公告)号：US20230111192A1

公开(公告)日：2023-04-13

申请号：US17527434

申请日：2021-11-16

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yi-Min Fu ,  Chi-Ching Ho ,  Cheng-Yu Kang ,  Yu-Po Wang

IPC: H01L23/498 ,  H01L23/367 ,  H01L21/48

Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.

公开(公告)号：US20180233442A1

公开(公告)日：2018-08-16

申请号：US15950734

申请日：2018-04-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Lin Tsai ,  Yi-Feng Chang ,  Cheng-Jen Liu ,  Yi-Min Fu ,  Hung-Chi Chen

IPC: H01L23/498 ,  H01L21/265 ,  H01L29/78 ,  H01L29/762 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/26533 ,  H01L21/486 ,  H01L29/762 ,  H01L29/7834 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.