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83 条记录 (耗时 0.026 秒)

    Avalanche impact ionization amplification devices
    11.
    发明授权
    Avalanche impact ionization amplification devices 有权
    雪崩冲击电离放大装置

    公开(公告)号：US08395103B2

    公开(公告)日：2013-03-12

    申请号：US13455507

    申请日：2012-04-25

    申请人： Solomon Assefa ,  Yurii A. Vlasov ,  Fengnian Xia

    发明人： Solomon Assefa ,  Yurii A. Vlasov ,  Fengnian Xia

    IPC分类号： H01L31/00 ,  H01L31/107

    CPC分类号： H01L31/107 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/03529 ,  Y02E10/50

    摘要： A semiconductor photodetector may provide charge carrier avalanche multiplication at high field regions of a semiconductor material layer. A semiconductor current amplifier may provide current amplification by impact ionization near a high field region. A plurality of metal electrodes are formed on a surface of a semiconductor material layer and electrically biased to produce a non-uniform high electric field in which the high electric field strength accelerates avalanche electron-hole pair generation, which is employed as an effective avalanche multiplication photodetection mechanism or as an avalanche impact ionization current amplification mechanism.

    摘要翻译： 半导体光电探测器可以在半导体材料层的高场区域提供电荷载体雪崩倍增。 半导体电流放大器可以通过在高场区域附近的冲击电离提供电流放大。 多个金属电极形成在半导体材料层的表面上并被电偏置以产生不均匀的高电场，其中高电场强度加速雪崩电子 - 空穴对产生，其被用作有效的雪崩倍增 光电检测机制或雪崩冲击电离电流放大机制。

    Avalanche impact ionization amplification devices
    13.
    发明授权
    Avalanche impact ionization amplification devices 有权
    雪崩冲击电离放大装置

    公开(公告)号：US08232516B2

    公开(公告)日：2012-07-31

    申请号：US12533521

    申请日：2009-07-31

    申请人： Solomon Assefa ,  Yurii A. Vlasov ,  Fengnian Xia

    发明人： Solomon Assefa ,  Yurii A. Vlasov ,  Fengnian Xia

    IPC分类号： H01L31/00 ,  H01L31/107

    CPC分类号： H01L31/107 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/03529 ,  Y02E10/50

    摘要： A semiconductor photodetector may provide charge carrier avalanche multiplication at high field regions of a semiconductor material layer. A semiconductor current amplifier may provide current amplification by impact ionization near a high field region. A plurality of metal electrodes are formed on a surface of a semiconductor material layer and electrically biased to produce a non-uniform high electric field in which the high electric field strength accelerates avalanche electron-hole pair generation, which is employed as an effective avalanche multiplication photodetection mechanism or as an avalanche impact ionization current amplification mechanism.

    摘要翻译： 半导体光电探测器可以在半导体材料层的高场区域提供电荷载体雪崩倍增。 半导体电流放大器可以通过在高场区域附近的冲击电离提供电流放大。 多个金属电极形成在半导体材料层的表面上并被电偏置以产生不均匀的高电场，其中高电场强度加速雪崩电子 - 空穴对产生，其被用作有效的雪崩倍增 光电检测机制或雪崩冲击电离电流放大机制。

    Three-dimensional integrated circuits and techniques for fabrication thereof
    14.
    发明授权
    Three-dimensional integrated circuits and techniques for fabrication thereof 有权
    三维集成电路及其制造技术

    公开(公告)号：US07897428B2

    公开(公告)日：2011-03-01

    申请号：US12131988

    申请日：2008-06-03

    申请人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    发明人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    IPC分类号： H01L27/12

    CPC分类号： H01L27/0688 ,  H01L25/167 ,  H01L27/144 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

    摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

    摘要翻译： 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，三维集成电路包括底部器件层和顶部器件层。 底部器件层包括衬底; 与衬底相邻的数字CMOS电路层; 以及与数字CMOS电路层的与衬底相对的一侧相邻的第一结合氧化物层。 顶部器件层包括形成在具有大于或等于约0.5微米厚度的掩埋氧化物（BOX）的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层; 以及与模拟CMOS和光子电路层相邻的第二键合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

    Techniques for Three-Dimensional Circuit Integration
    15.
    发明申请
    Techniques for Three-Dimensional Circuit Integration 有权
    三维电路集成技术

    公开(公告)号：US20090297091A1

    公开(公告)日：2009-12-03

    申请号：US12132029

    申请日：2008-06-03

    申请人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    发明人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    IPC分类号： G02B6/12 ,  H01L21/84 ,  H01L27/12

    CPC分类号： H01L27/0688

    摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

    摘要翻译： 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，一种三维集成电路包括底部器件层和顶部器件层。 底部器件层包括数字CMOS电路层; 以及与数字CMOS电路层相邻的第一结合氧化物层。 顶部器件层包括衬底; 形成在与衬底相邻的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层，所述SOI层具有厚度大于或等于约1微米的掩埋氧化物（BOX）; 以及与模拟CMOS和与衬底相对的光子电路层的一侧相邻的第二结合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

    Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof
    16.
    发明申请
    Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof 有权
    三维集成电路及其制造技术

    公开(公告)号：US20090294814A1

    公开(公告)日：2009-12-03

    申请号：US12131988

    申请日：2008-06-03

    申请人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    发明人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    IPC分类号： H01L31/00 ,  H01L21/00

    CPC分类号： H01L27/0688 ,  H01L25/167 ,  H01L27/144 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

    摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

    摘要翻译： 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，三维集成电路包括底部器件层和顶部器件层。 底部器件层包括衬底; 与衬底相邻的数字CMOS电路层; 以及与数字CMOS电路层的与衬底相对的一侧相邻的第一结合氧化物层。 顶部器件层包括形成在具有大于或等于约0.5微米厚度的掩埋氧化物（BOX）的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层; 以及与模拟CMOS和光子电路层相邻的第二结合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

    Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit
    18.
    发明申请
    Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit 有权
    利用侧壁间隔物特征在集成电路中形成磁隧道结

    公开(公告)号：US20070166840A1

    公开(公告)日：2007-07-19

    申请号：US11333997

    申请日：2006-01-18

    申请人： Solomon Assefa ,  Michael Gaidis ,  Sivananda Kanakasabapathy ,  John Hummel ,  David Abraham

    发明人： Solomon Assefa ,  Michael Gaidis ,  Sivananda Kanakasabapathy ,  John Hummel ,  David Abraham

    IPC分类号： H01L21/00 ,  H01L29/94

    CPC分类号： H01L43/12 ,  H01L27/222

    摘要： Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.

    摘要翻译： 描述了在集成电路中可靠且可重复地形成磁隧道结的新方法。 根据本发明的方面，在膜叠层的处理期间利用侧壁间隔物特征。 有利地，这些侧壁间隔物特征产生锥形掩蔽特征，其有助于避免在MTJ膜叠层的蚀刻期间的副产物再沉积，从而提高工艺产率。 此外，侧壁间隔物特征可以在随后的处理步骤期间用作包封层，并且可以用作垂直接触以进行更高级别的金属化。