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    Integration of buried oxide layers with crystalline layers
    1.
    发明申请
    Integration of buried oxide layers with crystalline layers 有权
    将掩埋氧化物层与结晶层集成

    公开(公告)号：US20060276002A1

    公开(公告)日：2006-12-07

    申请号：US11433736

    申请日：2006-05-12

    申请人： Sheila Tandon ,  Gale Petrich ,  Leslie Kolodziejski

    发明人： Sheila Tandon ,  Gale Petrich ,  Leslie Kolodziejski

    IPC分类号： H01L21/76

    CPC分类号： G02F1/3523 ,  G02F2201/346 ,  H01L33/10 ,  H01S3/1118 ,  H01S5/18311 ,  H01S5/18372

    摘要： A method of forming a buried oxide/crystalline III-V semiconductor dielectric stack is presented. The method includes providing a substrate and forming a layered structure on the substrate comprising of layers of different materials, one of the different materials is selected to be an oxidizable material to form one or more buried low index oxide layers. A first sequence of oxidizing steps are performed on the layered structure by exposing the edges of the layered structure to a succession of temperature increases in the presence of steam from an initial temperature to the desired oxidation temperature for a time interval equal to the sum of the time intervals of the succession of temperature increases. Also, the method includes performing a second sequential oxidizing step with steam on the layered structure at the specific oxidation temperature for a specific time interval. Furthermore, the method includes performing a final sequence of oxidizing steps on the structure by ramping down from the desired oxidation temperature to a final temperature when the oxidizing material is completely oxidized to form the one or more buried low index oxide layers.

    摘要翻译： 提出了形成掩埋氧化物/晶体III-V半导体电介质堆叠的方法。 该方法包括提供衬底并在包括不同材料的层的衬底上形成层状结构，不同材料之一被选择为可氧化材料以形成一个或多个掩埋的低折射率氧化物层。 通过将层状结构的边缘暴露于蒸汽存在下的一连串的温度升高，在层状结构上进行第一序列氧化步骤，时间间隔等于初始温度至期望的氧化温度 温度连续的时间间隔增加。 此外，该方法包括在特定氧化温度下在特定时间间隔内在层状结构上用蒸汽进行第二顺序氧化步骤。 此外，该方法包括当氧化材料被完全氧化以形成一个或多个掩埋的低折射率氧化物层时，通过从期望的氧化温度向下倾斜到最终温度，在结构上执行最终的氧化步骤序列。

    Integration of buried oxide layers with crystalline layers
    2.
    发明授权
    Integration of buried oxide layers with crystalline layers 有权
    将掩埋氧化物层与结晶层集成

    公开(公告)号：US08008215B2

    公开(公告)日：2011-08-30

    申请号：US11433736

    申请日：2006-05-12

    申请人： Sheila Tandon ,  Gale Petrich ,  Leslie Kolodziejski

    发明人： Sheila Tandon ,  Gale Petrich ,  Leslie Kolodziejski

    IPC分类号： H01L21/31

    CPC分类号： G02F1/3523 ,  G02F2201/346 ,  H01L33/10 ,  H01S3/1118 ,  H01S5/18311 ,  H01S5/18372

    摘要： A method of forming a buried oxide/crystalline III-V semiconductor dielectric stack is presented. The method includes providing a substrate and forming a layered structure on the substrate comprising of layers of different materials, one of the different materials is selected to be an oxidizable material to form one or more buried low index oxide layers. A first sequence of oxidizing steps are performed on the layered structure by exposing the edges of the layered structure to a succession of temperature increases in the presence of steam from an initial temperature to the desired oxidation temperature for a time interval equal to the sum of the time intervals of the succession of temperature increases. Also, the method includes performing a second sequential oxidizing step with steam on the layered structure at the specific oxidation temperature for a specific time interval. Furthermore, the method includes performing a final sequence of oxidizing steps on the structure by ramping down from the desired oxidation temperature to a final temperature when the oxidizing material is completely oxidized to form the one or more buried low index oxide layers.

    摘要翻译： 提出了形成掩埋氧化物/晶体III-V半导体电介质堆叠的方法。 该方法包括提供衬底并在包括不同材料的层的衬底上形成层状结构，不同材料之一被选择为可氧化材料以形成一个或多个掩埋的低折射率氧化物层。 通过将层状结构的边缘暴露于蒸汽存在下的一连串的温度升高，在层状结构上进行第一序列氧化步骤，时间间隔等于初始温度至期望的氧化温度 温度连续的时间间隔增加。 此外，该方法包括在特定氧化温度下在特定时间间隔内在层状结构上用蒸汽进行第二顺序氧化步骤。 此外，该方法包括当氧化材料被完全氧化以形成一个或多个掩埋的低折射率氧化物层时，通过从期望的氧化温度向下倾斜到最终温度，在结构上执行最终的氧化步骤序列。

    Composite photonic crystals
    4.
    发明授权
    Composite photonic crystals 失效
    复合光子晶体

    公开(公告)号：US06134043A

    公开(公告)日：2000-10-17

    申请号：US132580

    申请日：1998-08-11

    申请人： Steven G. Johnson ,  Shanhui Fan ,  Pierre R. Villeneuve ,  Leslie Kolodziejski ,  John D. Joannopoulos

    发明人： Steven G. Johnson ,  Shanhui Fan ,  Pierre R. Villeneuve ,  Leslie Kolodziejski ,  John D. Joannopoulos

    IPC分类号： G02B6/12 ,  C30B33/00 ,  G02B6/122 ,  G02B26/00

    CPC分类号： C30B33/00 ,  B82Y20/00 ,  C30B29/60 ,  G02B6/1225

    摘要： A composite photonic crystal structure comprising a guide crystal configured in a lane having a dielectric periodicity in at least a first direction in the plane; and barrier crystals configured above and below the guide crystal to confine light within the guide crystal, the barrier crystals having a dielectric periodicity in at least a second direction not in the plane. In another embodiment, there is provided a composite photonic crystal structure comprising a guide crystal configured in a plane having a dielectric periodicity in at least one dimension; and a barrier crystal configured adjacent the guide crystal to confine light within the guide crystal, the barrier crystal having a dielectric periodicity in at least two dimensions.

    摘要翻译： 一种复合光子晶体结构，包括在平面中在至少第一方向上具有介电周期的通道中构造的引导晶体; 以及配置在引导晶体的上方和下方的阻挡晶体，以将光限制在引导晶体内，所述阻挡晶体在不在平面中的至少第二方向上具有介电周期性。 在另一个实施例中，提供一种复合光子晶体结构，其包括在至少一个维度上具有介电周期的平面中构造的引导晶体; 以及与引导晶体相邻配置以将光限制在引导晶体内的阻挡晶体，所述阻挡晶体在至少两个维度上具有介电周期性。