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    TRANSISTOR WITH BOOT SHAPED SOURCE/DRAIN REGIONS
    12.
    发明申请
    TRANSISTOR WITH BOOT SHAPED SOURCE/DRAIN REGIONS 有权
    带引导形状源/漏区的晶体管

    公开(公告)号：US20130032864A1

    公开(公告)日：2013-02-07

    申请号：US13204271

    申请日：2011-08-05

    申请人： Peter Javorka ,  Stephan D. Kronholz ,  Matthias Kessler ,  Roman Boschke

    发明人： Peter Javorka ,  Stephan D. Kronholz ,  Matthias Kessler ,  Roman Boschke

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/6653 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    摘要： Devices are formed with boot shaped source/drain regions formed by isotropic etching followed by anisotropic etching. Embodiments include forming a gate on a substrate, forming a first spacer on each side of the gate, forming a source/drain region in the substrate on each side of the gate, wherein each source/drain region extends under a first spacer, but is separated therefrom by a portion of the substrate, and has a substantially horizontal bottom surface. Embodiments also include forming each source/drain region by forming a cavity to a first depth adjacent the first spacer and forming a second cavity to a second depth below the first cavity and extending laterally underneath the first spacers.

    摘要翻译： 器件形成有通过各向同性蚀刻然后进行各向异性蚀刻形成的引线形状的源极/漏极区域。 实施例包括在衬底上形成栅极，在栅极的每一侧上形成第一间隔物，在栅极的每一侧上在衬底中形成源极/漏极区域，其中每个源极/漏极区域在第一间隔物之下延伸，但是 由基板的一部分与之隔开，并具有基本上水平的底面。 实施例还包括通过将空腔形成为与第一间隔件相邻的第一深度并形成第二腔至第一腔的第二深度并且在第一间隔物下方横向延伸来形成每个源/漏区。

    Ionization Method, Ion Producing Device and Uses of the Same in Ion Mobility Spectrometry
    14.
    发明申请
    Ionization Method, Ion Producing Device and Uses of the Same in Ion Mobility Spectrometry 有权
    电离法，离子生成装置及其在离子流动性光谱法中的应用

    公开(公告)号：US20120235032A1

    公开(公告)日：2012-09-20

    申请号：US13499506

    申请日：2010-08-26

    申请人： Johann Goebel ,  Andreas Langmeier ,  Matthias Kessler

    发明人： Johann Goebel ,  Andreas Langmeier ,  Matthias Kessler

    IPC分类号： H01J49/26 ,  H01J27/24 ,  H01J27/02

    CPC分类号： H01J49/0027 ,  G01N27/64 ,  H01J49/0031 ,  H01J49/162

    摘要： A method for ionizing, using pulses of ionization radiation, an analyte to be examined by way of ion mobility spectrometry using a pulse sequence is modulated with a known time-variable impression pattern is provided. An ionization device for carrying out the method and an ion mobility spectrometry method and an ion mobility spectrometry device that use the ionization method and/or the ionization device are also provided.

    摘要翻译： 提供了使用脉冲序列离子化电离辐射待测分析物的方法，该分析物通过离子迁移光谱法被调制，并且已知的时间变化的印模模式被调制。 还提供了用于实施该方法的离子化装置和使用该离子化方法和/或电离装置的离子迁移谱分析方法和离子迁移率光谱测定装置。

    Semiconductor device comprising metal-based eFuses of enhanced programming efficiency by enhancing heat generation
    15.
    发明授权
    Semiconductor device comprising metal-based eFuses of enhanced programming efficiency by enhancing heat generation 有权
    半导体器件包括通过增强发热而提高编程效率的基于金属的eFuse

    公开(公告)号：US09287211B2

    公开(公告)日：2016-03-15

    申请号：US13032710

    申请日：2011-02-23

    申请人： Andreas Kurz ,  Jens Poppe ,  Matthias Kessler

    发明人： Andreas Kurz ,  Jens Poppe ,  Matthias Kessler

    IPC分类号： H01L23/535 ,  H01L29/00 ,  H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： In sophisticated semiconductor devices, electronic fuses may be provided in the metallization system, wherein a superior two-dimensional configuration of the metal line, for instance as a helix-like configuration, may provide superior thermal conditions in a central line portion, which in turn may result in a more pronounced electromigration effect for a given programming current. Consequently, the size of the electronic fuse, at least in one lateral direction, and also the width of corresponding transistors connected to the electronic fuse, may be reduced.

    摘要翻译： 在复杂的半导体器件中，可以在金属化系统中提供电子熔丝，其中金属线的优越的二维结构，例如螺旋状结构，可以在中心线部分提供优异的热条件，反过来 可能导致给定编程电流更显着的电迁移效应。 因此，至少在一个横向方向上的电子熔断器的尺寸以及连接到电子熔断器的相应的晶体管的宽度可以减小。

    METHODS OF FORMING TRANSISTOR DEVICES WITH HIGH-K INSULATION LAYERS AND THE RESULTING DEVICES
    18.
    发明申请
    METHODS OF FORMING TRANSISTOR DEVICES WITH HIGH-K INSULATION LAYERS AND THE RESULTING DEVICES 有权
    用高K绝缘层和结晶器件形成晶体管器件的方法

    公开(公告)号：US20140027859A1

    公开(公告)日：2014-01-30

    申请号：US13561315

    申请日：2012-07-30

    申请人： Martin Gerhardt ,  Stefan Flachowsky ,  Matthias Kessler

    发明人： Martin Gerhardt ,  Stefan Flachowsky ,  Matthias Kessler

    IPC分类号： H01L21/28 ,  H01L27/088

    CPC分类号： H01L27/088 ,  H01L21/28202 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

    摘要： Method of forming transistor devices is disclosed that includes forming a first layer of high-k insulating material and a sacrificial protection layer above first and second active regions, removing the first layer of insulating material and the protection layer from above the second active region, removing the protection layer from above the first layer of insulating material positioned above the first active region, forming a second layer of high-k insulating material above the first layer of insulating material and the second active region, forming a layer of metal above the second layer of insulating material, and removing portions of the first and second layers of insulating material and the metal layer to form a first gate stack (comprised of the first and second layers of high-k material and the layer of metal) and a second gate stack (comprised of the second layer of high-k material and the layer of metal).

    摘要翻译： 公开了形成晶体管器件的方法，其包括在第一和第二有源区之上形成第一层高k绝缘材料和牺牲保护层，从第二有源区上方去除第一绝缘材料层和保护层，去除 所述保护层位于所述第一绝缘材料层上方，位于所述第一有源区上方，在所述第一绝缘材料层和所述第二有源区上方形成第二层高k绝缘材料，在所述第二层上方形成金属层 的绝缘材料，并且去除第一和第二绝缘材料层和金属层的部分以形成第一栅极叠层（由第一和第二层高k材料和金属层组成）和第二栅极堆叠 （由第二层高k材料和金属层组成）。

    Transistor with boot shaped source/drain regions
    19.
    发明授权
    Transistor with boot shaped source/drain regions 有权
    具有引导形状的源极/漏极区域的晶体管

    公开(公告)号：US08497180B2

    公开(公告)日：2013-07-30

    申请号：US13204271

    申请日：2011-08-05

    申请人： Peter Javorka ,  Stephan D. Kronholz ,  Matthias Kessler ,  Roman Boschke

    发明人： Peter Javorka ,  Stephan D. Kronholz ,  Matthias Kessler ,  Roman Boschke

    IPC分类号： H01L21/00 ,  H01L21/02

    CPC分类号： H01L29/6653 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    摘要： Devices are formed with boot shaped source/drain regions formed by isotropic etching followed by anisotropic etching. Embodiments include forming a gate on a substrate, forming a first spacer on each side of the gate, forming a source/drain region in the substrate on each side of the gate, wherein each source/drain region extends under a first spacer, but is separated therefrom by a portion of the substrate, and has a substantially horizontal bottom surface. Embodiments also include forming each source/drain region by forming a cavity to a first depth adjacent the first spacer and forming a second cavity to a second depth below the first cavity and extending laterally underneath the first spacers.

    摘要翻译： 器件形成有通过各向同性蚀刻然后进行各向异性蚀刻形成的引线形状的源极/漏极区域。 实施例包括在衬底上形成栅极，在栅极的每一侧上形成第一间隔物，在栅极的每一侧上在衬底中形成源极/漏极区域，其中每个源极/漏极区域在第一间隔物之下延伸，但是 由基板的一部分与之隔开，并具有基本上水平的底面。 实施例还包括通过将空腔形成为与第一间隔件相邻的第一深度并形成第二腔至第一腔的第二深度并且在第一间隔物下方横向延伸来形成每个源/漏区。

    Methods of Forming Source/Drain Regions on Transistor Devices
    20.
    发明申请
    Methods of Forming Source/Drain Regions on Transistor Devices 审中-公开
    在晶体管器件上形成源极/漏极区域的方法

    公开(公告)号：US20130095627A1

    公开(公告)日：2013-04-18

    申请号：US13275967

    申请日：2011-10-18

    申请人： Stefan Flachowsky ,  Matthias Kessler ,  Martin Gerhardt

    发明人： Stefan Flachowsky ,  Matthias Kessler ,  Martin Gerhardt

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66636

    摘要： The present disclosure is directed to various methods of forming source/drain regions for transistor devices. In one example, a method disclosed herein includes the steps of forming a gate electrode structure for a transistor above a semiconducting substrate, performing a first etching process to define a plurality of initial cavities in the substrate proximate the gate structure for the transistor and after forming the initial cavities, performing an anneal process. The method continues with the steps of, after performing the anneal process, performing a second etching process on the initial cavities to define a plurality of final cavities and forming a semiconductor material in the final cavities.

    摘要翻译： 本公开涉及为晶体管器件形成源极/漏极区域的各种方法。 在一个示例中，本文公开的方法包括以下步骤：在半导体衬底上形成用于晶体管的栅电极结构，执行第一蚀刻工艺以在晶体管的栅极结构附近限定衬底中的多个初始腔，并且在形成之后 初始腔，进行退火处理。 该方法继续以下步骤：在执行退火处理之后，对初始空腔执行第二蚀刻工艺以限定多个最终空腔并在最终空腔中形成半导体材料。