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    Technique and apparatus for combining partial write transactions
    12.
    发明申请
    Technique and apparatus for combining partial write transactions 审中-公开
    用于组合部分写入事务的技术和装置

    公开(公告)号：US20080235461A1

    公开(公告)日：2008-09-25

    申请号：US11726563

    申请日：2007-03-22

    Applicant: Sin Tan ,  Kai Cheng ,  Rajesh S. Pamujula ,  Sivakumar Radhakrishnan ,  Dhananjay Joshi

    Inventor： Sin Tan ,  Kai Cheng ,  Rajesh S. Pamujula ,  Sivakumar Radhakrishnan ,  Dhananjay Joshi

    IPC: G06F13/28

    CPC classification number: G06F13/1663 ,  G06F13/1668

    Abstract: A bridge includes a memory to establish a transaction table and write combining windows. Each write combining window is associated with a cache line and is subdivided into subwindows; and each of the subwindows is associated with a partial cache line. The bridge includes a controller to determine whether an incoming partial write transaction conflicts with a transaction stored in the transaction table. If a conflict occurs, the controller uses the write combining windows to combine the partial write transaction with another partial write transaction if one of the partial write combining windows is available. The controller issues a retry signal to a processor originating the partial write transaction if none of the partial write combining windows are available.

    Abstract translation: 一个桥包括一个建立事务表和写入组合窗口的内存。 每个写入组合窗口与高速缓存行相关联，并被细分为子窗口; 并且每个子窗口与部分高速缓存行相关联。 该桥包括一个控制器，用于确定传入的部分写入事务是否与存储在事务表中的事务冲突。 如果发生冲突，则如果部分写入组合窗口之一可用，则控制器使用写入组合窗口将部分写入事务与另一个部分写入事务组合。 如果没有部分写入组合窗口可用，则控制器向发起部分写入事务的处理器发出重试信号。

    Chipset feature detection and configuration by an I/O device
    13.
    发明授权
    Chipset feature detection and configuration by an I/O device 有权
    芯片组特征检测和I / O设备配置

    公开(公告)号：US07363393B2

    公开(公告)日：2008-04-22

    申请号：US10750060

    申请日：2003-12-30

    Applicant: William T. Futral ,  Kenneth C. Creta ,  Sujoy Sen ,  Gregory D. Cummings ,  Sivakumar Radhakrishnan

    Inventor： William T. Futral ,  Kenneth C. Creta ,  Sujoy Sen ,  Gregory D. Cummings ,  Sivakumar Radhakrishnan

    IPC: G06F3/00

    CPC classification number: G06F13/4027

    Abstract: Apparatus and method for a first device to query a second device for the availability of a hardware feature within the second device, and for the second to receive and analyze the query to determine whether or not to respond, depending on the version of hardware feature sought, a code identifying a vendor, etc., and responding with a reply providing an indication of availability of the hardware feature and/or an address at which the hardware feature may be accessed, if the determination is made to reply.

    Abstract translation: 用于第一设备的第二设备查询第二设备内的硬件特征的可用性的装置和方法，以及第二设备接收和分析查询以确定是否响应，取决于所寻求的硬件特征的版本 ，识别供应商等的代码，并且如果确定作出回复，则响应提供硬件特征的可用性的指示和/或可以访问硬件特征的地址。

    Method, apparatus and system to generate an interrupt by monitoring an external interface
    14.
    发明申请
    Method, apparatus and system to generate an interrupt by monitoring an external interface 有权
    通过监视外部接口产生中断的方法，装置和系统

    公开(公告)号：US20060143351A1

    公开(公告)日：2006-06-29

    申请号：US11025381

    申请日：2004-12-28

    Applicant: David Lee ,  Steve Kulick ,  Sivakumar Radhakrishnan

    Inventor： David Lee ,  Steve Kulick ,  Sivakumar Radhakrishnan

    IPC: G06F13/24

    CPC classification number: G06F13/22 ,  G06F13/24

    Abstract: In some embodiments, a method, apparatus and system to generate an interrupt by monitoring an external interface are presented. In this regard, an interrupt agent is introduced to communicate over a serial interface with an input/output (I/O) extender and to save a relevant status of the I/O extender in a memory. Other embodiments are also disclosed and claimed.

    Abstract translation: 在一些实施例中，呈现通过监视外部接口来产生中断的方法，装置和系统。 在这方面，引入一个中断代理程序通过串行接口与输入/输出（I / O）扩展器进行通信，并将I / O扩展器的相关状态保存在存储器中。 还公开并要求保护其他实施例。

    Dynamic squelch detection power control
    18.
    发明申请
    Dynamic squelch detection power control 失效
    动态静噪检测功率控制

    公开(公告)号：US20100081406A1

    公开(公告)日：2010-04-01

    申请号：US12286188

    申请日：2008-09-29

    Applicant: Sin Tan ,  Sivakumar Radhakrishnan ,  Bruce A. Tennant ,  Jasper Balraj ,  Altug Koker

    Inventor： Sin Tan ,  Sivakumar Radhakrishnan ,  Bruce A. Tennant ,  Jasper Balraj ,  Altug Koker

    IPC: H04B1/10

    CPC classification number: G06F1/3287 ,  G06F1/3209 ,  Y02D10/171 ,  Y02D50/20

    Abstract: In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括用于静噪检测电路的功率控制逻辑，以使得能够以低功率模式选择性地启用互连接口的一个或多个静噪检测电路。 逻辑可以包括静噪模式控制寄存器以选择第一模式或第二模式的功率控制;第二寄存器，耦合到静噪模式控制寄存器以接收软件设置，以指示哪个静噪检测电路在低电平中禁用 互连的功率状态，以及用于在第二模式中动态地检测互连的逻辑通道零点的检测器。 描述和要求保护其他实施例。

    Maximal length packets
    19.
    发明授权
    Maximal length packets 有权
    最大长度数据包

    公开(公告)号：US07500029B2

    公开(公告)日：2009-03-03

    申请号：US10977230

    申请日：2004-10-29

    Applicant: Sivakumar Radhakrishnan ,  Siva Balasubramanian ,  Sin S. Tan ,  Suneeta Sah

    Inventor： Sivakumar Radhakrishnan ,  Siva Balasubramanian ,  Sin S. Tan ,  Suneeta Sah

    IPC: G06F3/00

    CPC classification number: G06F13/385

    Abstract: Detecting and flushing maximal length packets is set forth herein. In one embodiment, the method comprises receiving a flushing event and, in response to the flushing event, repeatedly detecting a maximum length packet of write data from a write combining storage area and flushing the detected maximum length packet to a target input/output (I/O) device over a bus. Each maximal length packet is a packet of maximum payload of write data that can be formulated within in the write combining storage area while adhering to packet protocol rules for the bus.

    Abstract translation: 本文阐述了检测和刷新最大长度数据包。 在一个实施例中，该方法包括接收冲洗事件，并且响应于冲洗事件，重复地从写入组合存储区域检测写入数据的最大长度分组，并将检测到的最大长度分组刷新到目标输入/输出（I / O）设备。 每个最大长度分组是写入数据的最大有效载荷的分组，其可以在遵守用于总线的分组协议规则的情况下在写入组合存储区域中被表达。

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