公开(公告)号：US07673087B1

公开(公告)日：2010-03-02

申请号：US12057322

申请日：2008-03-27

Applicant: Ahmad R. Ansari ,  Jeffery H. Applebaum ,  Kunal R. Shenoy

Inventor： Ahmad R. Ansari ,  Jeffery H. Applebaum ,  Kunal R. Shenoy

IPC: G06F13/14

CPC classification number: G06F13/366 ,  Y10S370/911

Abstract: Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.

Abstract translation: 描述了处理器块核心的仲裁。 主设备与嵌入在主机集成电路（“IC”）中的处理器块核心相关联。 主设备通过作为处理器块核心的一部分的交叉开关和桥接器耦合到主机IC的核心逻辑。 交叉开关包括仲裁器。 仲裁协议是从仲裁器中使用的仲裁协议中选出的。 被审查的待处理事务被轮询以使用所选择的仲裁协议访问该桥以进行仲裁。

公开(公告)号：US07200723B1

公开(公告)日：2007-04-03

申请号：US10913282

申请日：2004-08-06

Applicant: Ahmad R. Ansari ,  Kathryn Story Purcell

Inventor： Ahmad R. Ansari ,  Kathryn Story Purcell

IPC: G06F12/00

CPC classification number: G06F12/063 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/355 ,  G06F9/3822 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3897

Abstract: An interface for accessing a bank of registers is described. A controller is coupled to receive address information, read information and write information. The device control register interface includes: a data bus for receiving data, pointer information and operation delineation information; a decoder coupled to receive the read information, the write information, the pointer information and the operation delineation information, where the decoder is configured to provide activation signaling responsive to information received; and the bank of registers coupled to the decoder to receive the activation signaling and coupled to the data bus for receiving the data, where the address information is for the bank or registers and where a single address is used for accessing all registers in the bank of registers.

Abstract translation: 描述用于访问一组寄存器的接口。 控制器被耦合以接收地址信息，读取信息和写入信息。 设备控制寄存器接口包括：用于接收数据的数据总线，指针信息和操作描画信息; 耦合以接收读取信息，写入信息，指针信息和操作描绘信息的解码器，其中解码器被配置为响应于所接收的信息提供激活信令; 以及耦合到解码器的寄存器组，以接收激活信令并耦合到数据总线以接收数据，其中地址信息用于存储体或寄存器，并且其中单个地址用于访问存储体中的所有寄存器 注册

公开(公告)号：US08019950B1

公开(公告)日：2011-09-13

申请号：US12056954

申请日：2008-03-27

Applicant: Alex S. Warshofsky ,  Ahmad R. Ansari

Inventor： Alex S. Warshofsky ,  Ahmad R. Ansari

IPC: G06F13/00

CPC classification number: G06F13/1642 ,  G06F13/1678 ,  G06F2213/0038

Abstract: A method for address acknowledgement is described. A memory controller interface is embedded as part of an embedded core in a host integrated circuit. Access to the memory controller interface is arbitrated with an arbiter. An accept signal is sent from the memory controller interface to the arbiter to indicate whether the memory controller interface is ready to receive a transaction. Access to the memory controller interface is requested by a master device for passing the transaction to a memory controller via the arbiter. The arbiter is a proxy for the memory controller interface responsive to the accept signal being asserted. An acknowledgement signal is sent from the arbiter as a proxy for the memory controller interface responsive to receipt of the transaction and the accept signal being asserted.

Abstract translation: 描述地址确认的方法。 存储器控制器接口作为嵌入式核心的一部分嵌入在主机集成电路中。 存储器控制器接口的访问由仲裁器仲裁。 接收信号从存储器控制器接口发送到仲裁器，以指示存储器控制器接口是否准备好接收事务。 由主设备请求对存储器控制器接口的访问，以通过仲裁器将事务传递到存储器控制器。 仲裁器是响应于接受信号被断言的存储器控​​制器接口的代理。 响应于接收到交易并且接受信号被断言，确认信号作为代理存储器控制器接口从仲裁器发送。

公开(公告)号：US07970977B1

公开(公告)日：2011-06-28

申请号：US12363610

申请日：2009-01-30

Applicant: Kam-Wing Li ,  Ahmad R. Ansari ,  Sanford L. Helton ,  Tomai Knopp ,  Khang Kim Dao ,  Jeffrey H. Seltzer

Inventor： Kam-Wing Li ,  Ahmad R. Ansari ,  Sanford L. Helton ,  Tomai Knopp ,  Khang Kim Dao ,  Jeffrey H. Seltzer

IPC: G06F13/36 ,  G06F3/00 ,  G06F5/00 ,  G06F9/26

CPC classification number: G06F13/4036

Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Abstract translation: 桥接总线桥内的多个总线的方法可以包括确定总线桥的队列是否包括指向受限地址范围的事务请求，并且对于每个接收的事务请求，确定事务请求的地址是否为 指示在受限地址范围内。 可以根据交易请求所针对的地址是否在受限地址范围内以及该队列是否包括指向受限地址范围的交易请求，来选择性地拒绝总线桥接器接收的每个交易请求。

公开(公告)号：US06973405B1

公开(公告)日：2005-12-06

申请号：US10153980

申请日：2002-05-22

Applicant: Ahmad R. Ansari

Inventor： Ahmad R. Ansari

IPC: G06F11/263 ,  G06F11/277

CPC classification number: G06F11/263

Abstract: A verification agent can be used to verify hard and/or soft modules under test in an integrated circuit. The integrated circuit contains a processor and memory for storing code executable by the processor. The module under test performs predetermined operations. The verification agent interacts with the module under test, including sending signals to the module under test and generating results based on the interaction. The code causes the processor to receive the results and compare the results with expected values. The module under test may be deemed to operate properly if the actual results match the expected values.

Abstract translation: 验证代理可用于在集成电路中验证被测试的硬和/或软模块。 集成电路包含处理器和用于存储可由处理器执行的代码的存储器。 被测模块执行预定的操作。 验证代理与被测模块进行交互，包括将信号发送给被测模块，并根据交互产生结果。 该代码使处理器接收结果并将结果与​​预期值进行比较。 如果实际结果符合预期值，则被测模块可能会被视为正常运行。

公开(公告)号：US07610469B2

公开(公告)日：2009-10-27

申请号：US10812323

申请日：2004-03-29

Applicant: Ahmad R. Ansari

Inventor： Ahmad R. Ansari

IPC: G06F9/345

CPC classification number: G06F9/30043 ,  G06F9/30087 ,  G06F9/3455 ,  G06F9/383 ,  G06F9/3861

Abstract: A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing a burst transfer include determining the starting address of the vector data to be transferred, the ending address of the vector data to be transferred, and whether the ending address of the vector data to be transferred is within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined based on the number of data elements to be transferred, the stride of the vector data to be transferred, and the width of the vector data elements to be transferred. When the amount of data to be transferred is divisible by a factor of two, the multiplication of the stride and width of the data elements is carried out by shifting. An address error exception occurs when the ending address of the vector data to be transferred is not within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined in parallel with determining the starting address of the vector data to be transferred.

Abstract translation: 用于处理计算机系统中的存储器和数据处理器之间的矢量数据传送的矢量传送单元。 向量数据传输指令被发布到向量传送单元中的指令队列。 用于执行突发传送的程序指令包括确定要传送的向量数据的起始地址，要传送的向量数据的结束地址以及要传送的向量数据的结束地址是否在同一虚拟存储器页内 作为起始地址。 要传送的矢量数据的结束地址基于要传送的数据元素的数量，要传送的矢量数据的步幅以及要传送的矢量数据元素的宽度来确定。 当要传送的数据量可以被二进制整数时，通过移位来执行数据元素的跨步和宽度的乘法。 要传送的向量数据的结束地址与起始地址不在同一虚拟内存页内时，会发生地址错误异常。 要确定要传送的矢量数据的起始地址并行确定要传送的矢量数据的结束地址。

公开(公告)号：US07590822B1

公开(公告)日：2009-09-15

申请号：US10912865

申请日：2004-08-06

Applicant: Kathryn Story Purcell ,  Ahmad R. Ansari

Inventor： Kathryn Story Purcell ,  Ahmad R. Ansari

IPC: G06F15/00

CPC classification number: G06F9/3867 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3897

Abstract: Method and apparatus for indicating to a coprocessor when the coprocessor can update internal register content thereof without negative repercussion to a processor is described. A controller is coupled between the coprocessor and a processor, where the controller is configured with a state machine to track the instruction through pipeline stages of the processor.

Abstract translation: 描述了当协处理器可以更新其内部寄存器内容而不对处理器的负面影响时向协处理器指示的方法和装置。 控制器耦合在协处理器和处理器之间，其中控制器配置有状态机以通过处理器的流水线阶段跟踪指令。

公开(公告)号：US07546441B1

公开(公告)日：2009-06-09

申请号：US10912844

申请日：2004-08-06

Applicant: Ahmad R. Ansari ,  Kathryn Story Purcell

Inventor： Ahmad R. Ansari ,  Kathryn Story Purcell

IPC: G06F9/00

CPC classification number: G06F9/3869 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3897

Abstract: A controller interface between a processor and a coprocessor is described. The controller is coupled to the processor to provide a processor interface for operating at a first frequency, where the first frequency is a frequency of operation of the processor. The controller is coupled to the coprocessor to provide a coprocessor interface for operating at a second frequency, where the second frequency is a frequency of operation of the coprocessor which is slower than or equal to the first frequency. The controller is configured to operate at both the first frequency and the second frequency providing in part handshaking between the processor and the coprocessor such that the processor does not have to be slowed down to the second frequency for operation with the coprocessor.

Abstract translation: 描述处理器和协处理器之间的控制器接口。 控制器耦合到处理器以提供用于以第一频率操作的处理器接口，其中第一频率是处理器的操作频率。 控制器耦合到协处理器以提供用于在第二频率下操作的协处理器接口，其中第二频率是协处理器的操作频率，其慢于或等于第一频率。 控制器被配置为在第一频率和第二频率两者下操作，部分地在处理器和协处理器之间进行握手，使得处理器不必被放慢到第二频率以与协处理器一起操作。

公开(公告)号：US07346759B1

公开(公告)日：2008-03-18

申请号：US10912897

申请日：2004-08-06

Applicant: Ahmad R. Ansari ,  Kathryn Story Purcell

Inventor： Ahmad R. Ansari ,  Kathryn Story Purcell

IPC: G06F15/76

CPC classification number: G06F9/3877 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/3867 ,  G06F9/3897

Abstract: Method and apparatus for a decoder interface for a processor and a coprocessor is described. An input instruction register stores an input instruction from the processor. Configuration instruction registers store instructions. Comparison/pointer logic coupled to the input instruction register and the configuration instruction registers is configured to compare the input instruction from the processor with the instructions stored in the configuration registers to determine if there is a match, and configured to provide a pointer associated with a configuration instruction register of the configuration instruction registers having a instruction of the instructions matching the input instruction, where the pointer has fewer bits than the input instruction.

Abstract translation: 描述了用于处理器和协处理器的解码器接口的方法和装置。 输入指令寄存器存储来自处理器的输入指令。 配置指令寄存器存储指令。 耦合到输入指令寄存器和配置指令寄存器的比较/指针逻辑被配置为将来自处理器的输入指令与存储在配置寄存器中的指令进行比较，以确定是否存在匹配，并且被配置为提供与 具有与输入指令匹配的指令的指令的配置指令寄存器的配置指令寄存器，其中指针具有比输入指令少的位。

公开(公告)号：US08769231B1

公开(公告)日：2014-07-01

申请号：US12182934

申请日：2008-07-30

Applicant: Ahmad R. Ansari ,  Jeffery H. Appelbaum ,  Kunal R. Shenoy

Inventor： Ahmad R. Ansari ,  Jeffery H. Appelbaum ,  Kunal R. Shenoy

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/00

CPC classification number: G06F3/0659 ,  G06F13/16 ,  G06F13/4022

Abstract: A crossbar switch device for a processor block ASIC core and a method for a flush-posted-write(s)-before-read mode thereof are described. Operation for the flush-posted-write(s)-before-read mode is set in a first processor block interface coupled to programmable logic fabric. At least one write command is sent from a transaction initiating device instantiated using the programmable logic fabric to the first processor block interface. The at least one write command is posted in the first processor block interface. At least one write command received is stored in a command queue of the crossbar switch device. A read command initiated by a microprocessor is sent to the crossbar switch device. The at least one write command has an address overlap with the read command with respect to a destination target. The read command is temporarily blocked in the crossbar switch device until a command phase of the at least one write command is completed.

Abstract translation: 描述了一种用于处理器块ASIC核心的交叉开关装置和用于其先前读取模式的冲洗写入方法。 在读写模式下的操作用于与可编程逻辑结构相连的第一个处理器模块接口。 从使用可编程逻辑结构实例化的事务发起设备向第一处理器块接口发送至少一个写入命令。 至少一个写命令被发布在第一处理器块接口中。 接收到的至少一个写命令被存储在交叉开关装置的命令队列中。 由微处理器启动的读命令被发送到交叉开关装置。 所述至少一个写入命令具有与所述读取命令相对于目标目标的地址重叠。 读取命令在交叉开关装置中被暂时阻止，直到至少一个写命令的命令阶段完成。