公开(公告)号：US08019950B1

公开(公告)日：2011-09-13

申请号：US12056954

申请日：2008-03-27

Applicant: Alex S. Warshofsky ,  Ahmad R. Ansari

Inventor： Alex S. Warshofsky ,  Ahmad R. Ansari

IPC: G06F13/00

CPC classification number: G06F13/1642 ,  G06F13/1678 ,  G06F2213/0038

Abstract: A method for address acknowledgement is described. A memory controller interface is embedded as part of an embedded core in a host integrated circuit. Access to the memory controller interface is arbitrated with an arbiter. An accept signal is sent from the memory controller interface to the arbiter to indicate whether the memory controller interface is ready to receive a transaction. Access to the memory controller interface is requested by a master device for passing the transaction to a memory controller via the arbiter. The arbiter is a proxy for the memory controller interface responsive to the accept signal being asserted. An acknowledgement signal is sent from the arbiter as a proxy for the memory controller interface responsive to receipt of the transaction and the accept signal being asserted.

Abstract translation: 描述地址确认的方法。 存储器控制器接口作为嵌入式核心的一部分嵌入在主机集成电路中。 存储器控制器接口的访问由仲裁器仲裁。 接收信号从存储器控制器接口发送到仲裁器，以指示存储器控制器接口是否准备好接收事务。 由主设备请求对存储器控制器接口的访问，以通过仲裁器将事务传递到存储器控制器。 仲裁器是响应于接受信号被断言的存储器控​​制器接口的代理。 响应于接收到交易并且接受信号被断言，确认信号作为代理存储器控制器接口从仲裁器发送。

公开(公告)号：US08185720B1

公开(公告)日：2012-05-22

申请号：US12043097

申请日：2008-03-05

Applicant: Ahmad R. Ansari ,  Jeffery H. Appelbaum ,  Kam-Wing Li ,  James J. Murray ,  Kathryn S. Purcell ,  Alex S. Warshofsky

Inventor： Ahmad R. Ansari ,  Jeffery H. Appelbaum ,  Kam-Wing Li ,  James J. Murray ,  Kathryn S. Purcell ,  Alex S. Warshofsky

IPC: G06F15/76

CPC classification number: G06F15/7889

Abstract: A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar interconnect. The crossbar interconnect provides pipelines for coupling the hardwired core to the programmable circuitry. The microprocessor, the crossbar interconnect, and the memory controller interface are all capable of operating at a first frequency of operation, and the memory controller interface is further capable of being set to operate at a second frequency of operation having an integer ratio with respect to the first frequency of operation. The crossbar interconnect is configured to direct transactions initiated by the microprocessor to the memory controller interface for accessing one or more memory devices coupled to the memory controller interface via a memory controller. Additional or other interfaces may be coupled to the crossbar interconnect.

Abstract translation: 硬连线核心嵌入具有可编程电路的集成电路中。 硬接线芯具有微处理器; 耦合到微处理器的处理器本地总线的交叉开关互连; 以及耦合到交叉开关互连的存储器控​​制器接口。 交叉连接提供用于将硬连线核心耦合到可编程电路的管线。 微处理器，交叉开关互连和存储器控制器接口都能够以第一操作频率操作，并且存储器控制器接口还能够被设置为在第二操作频率下操作，其具有相对于 第一个操作频率。 交叉开关互连被配置为将由微处理器发起的事务定向到存储器控制器接口，用于经由存储器控制器访问耦合到存储器控制器接口的一个或多个存储器件。 附加或其他接口可以耦合到交叉开关互连。

公开(公告)号：US07724028B1

公开(公告)日：2010-05-25

申请号：US12101375

申请日：2008-04-11

Applicant: Ahmad R. Ansari ,  Alex S. Warshofsky

Inventor： Ahmad R. Ansari ,  Alex S. Warshofsky

IPC: G06F7/38 ,  H03K19/173

CPC classification number: H03K19/1774 ,  G06F1/10 ,  H03K19/17732

Abstract: An ASIC block embedded in a host IC has a first clock domain with a first frequency of operation that is at least equal to a second frequency of operation of a second clock domain in the host IC but external to the ASIC block. FPGA logic in the second clock domain interfaces with the ASIC block; and a PLL located in the host integrated circuit but external to the ASIC block is coupled to receive a reference clock signal and configured to generate clock signals. Two of the clock signals are respectively sent to the FPGA logic and the ASIC block to make one appear to be produced earlier in time than the other with respect to the ASIC block to compensate for a clock insertion delay and for a clock-to-output time associated with the FPGA logic that at least approximates zero.

Abstract translation: 嵌入在主机IC中的ASIC块具有第一时钟域，其具有至少等于主机IC中的第二时钟域的第二频率的操作的第一操作频率，但是在ASIC块的外部。 第二个时钟域的FPGA逻辑与ASIC块接口; 并且位于主机集成电路中但在ASIC块外部的PLL被耦合以接收参考时钟信号并被配置为产生时钟信号。 时钟信号中的两个分别被发送到FPGA逻辑和ASIC块，以使它们相对于ASIC块在时间上比另一个稍早地产生，以补偿时钟插入延迟和时钟到输出 与FPGA逻辑相关的时间至少近似为零。

公开(公告)号：US08006021B1

公开(公告)日：2011-08-23

申请号：US12057326

申请日：2008-03-27

Applicant: Kam-Wing Li ,  Jeffery H. Appelbaum ,  Ahmad R. Ansari

Inventor： Kam-Wing Li ,  Jeffery H. Appelbaum ,  Ahmad R. Ansari

IPC: G06F13/36

CPC classification number: G06F13/4059

Abstract: A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.

Abstract translation: 描述了一种用于嵌入IC的处理器块ASIC核心的处理器局部总线桥。 核心逻辑到核心逻辑桥包括从处理器本地总线接口，耦合到从属处理器本地总线接口的交叉开关和耦合到交叉开关的主处理器本地总线接口。 从处理器本地总线接口和主处理器本地总线接口通过交叉开关彼此耦合，用于核心逻辑的第一和第二部分之间的双向通信。 桥接器提供用于桥接的速率适配，以使用与交叉开关相关联的操作频率，其具有比与主处理器和从属处理器局部总线接口的核心逻辑侧相关联的操作频率更大的操作频率。

公开(公告)号：US07737725B1

公开(公告)日：2010-06-15

申请号：US12098400

申请日：2008-04-04

Applicant: Ahmad R. Ansari ,  Kam-Wing Li

Inventor： Ahmad R. Ansari ,  Kam-Wing Li

IPC: G06F7/38 ,  H03K19/173

CPC classification number: G06F15/7867

Abstract: A device control register controller for a processor block Application Specific Integrated Circuit (“ASIC”) core is described. Device control register slave blocks are coupled to the device control register controller and have access to device registers for a plurality of interfaces of the processor block ASIC core. A master device interface is for coupling at least one slave device external to the processor block ASIC core to the device control register controller. A slave device interface is for coupling a master device external to the processor block ASIC core to the device control register controller.

Abstract translation: 描述了用于处理器块的设备控制寄存器控制器专用集成电路（“ASIC”）核心。 器件控制寄存器从器件块耦合到器件控制寄存器控制器，并且可以访问处理器块ASIC核心的多个接口的器件寄存器。 主设备接口用于将处理器块ASIC核心外部的至少一个从设备耦合到设备控制寄存器控制器。 从设备接口用于将处理器块ASIC核心外部的主设备耦合到设备控制寄存器控制器。

公开(公告)号：US07673087B1

公开(公告)日：2010-03-02

申请号：US12057322

申请日：2008-03-27

Applicant: Ahmad R. Ansari ,  Jeffery H. Applebaum ,  Kunal R. Shenoy

Inventor： Ahmad R. Ansari ,  Jeffery H. Applebaum ,  Kunal R. Shenoy

IPC: G06F13/14

CPC classification number: G06F13/366 ,  Y10S370/911

Abstract: Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.

Abstract translation: 描述了处理器块核心的仲裁。 主设备与嵌入在主机集成电路（“IC”）中的处理器块核心相关联。 主设备通过作为处理器块核心的一部分的交叉开关和桥接器耦合到主机IC的核心逻辑。 交叉开关包括仲裁器。 仲裁协议是从仲裁器中使用的仲裁协议中选出的。 被审查的待处理事务被轮询以使用所选择的仲裁协议访问该桥以进行仲裁。

公开(公告)号：US07200723B1

公开(公告)日：2007-04-03

申请号：US10913282

申请日：2004-08-06

Applicant: Ahmad R. Ansari ,  Kathryn Story Purcell

Inventor： Ahmad R. Ansari ,  Kathryn Story Purcell

IPC: G06F12/00

CPC classification number: G06F12/063 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/355 ,  G06F9/3822 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3897

Abstract: An interface for accessing a bank of registers is described. A controller is coupled to receive address information, read information and write information. The device control register interface includes: a data bus for receiving data, pointer information and operation delineation information; a decoder coupled to receive the read information, the write information, the pointer information and the operation delineation information, where the decoder is configured to provide activation signaling responsive to information received; and the bank of registers coupled to the decoder to receive the activation signaling and coupled to the data bus for receiving the data, where the address information is for the bank or registers and where a single address is used for accessing all registers in the bank of registers.

Abstract translation: 描述用于访问一组寄存器的接口。 控制器被耦合以接收地址信息，读取信息和写入信息。 设备控制寄存器接口包括：用于接收数据的数据总线，指针信息和操作描画信息; 耦合以接收读取信息，写入信息，指针信息和操作描绘信息的解码器，其中解码器被配置为响应于所接收的信息提供激活信令; 以及耦合到解码器的寄存器组，以接收激活信令并耦合到数据总线以接收数据，其中地址信息用于存储体或寄存器，并且其中单个地址用于访问存储体中的所有寄存器 注册

公开(公告)号：US06886092B1

公开(公告)日：2005-04-26

申请号：US10001871

申请日：2001-11-19

Applicant: Stephen M. Douglass ,  Ahmad R. Ansari

Inventor： Stephen M. Douglass ,  Ahmad R. Ansari

IPC: G06F9/38 ,  G06F9/44 ,  G06F15/00 ,  G06F15/78

CPC classification number: G06F15/7867 ,  G06F9/3877 ,  G06F9/3897

Abstract: A method and apparatus for processing data within a programmable gate array begins when a fixed logic processor that is embedded within the programmable gate array detects a custom operation code. The processing continues when the fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.

Abstract translation: 当可编程门阵列中嵌入的固定逻辑处理器检测到定制操作代码时，开始用于处理可编程门阵列内的数据的方法和装置。 当固定逻辑处理器向可编程门阵列提供自定义操作码的指示时，该处理继续。 该处理通过将可配置为专用处理器的可编程门阵列的至少一部分在从固定逻辑处理器接收到指示时执行固定逻辑例程而继续进行。

公开(公告)号：US07970977B1

公开(公告)日：2011-06-28

申请号：US12363610

申请日：2009-01-30

Applicant: Kam-Wing Li ,  Ahmad R. Ansari ,  Sanford L. Helton ,  Tomai Knopp ,  Khang Kim Dao ,  Jeffrey H. Seltzer

Inventor： Kam-Wing Li ,  Ahmad R. Ansari ,  Sanford L. Helton ,  Tomai Knopp ,  Khang Kim Dao ,  Jeffrey H. Seltzer

IPC: G06F13/36 ,  G06F3/00 ,  G06F5/00 ,  G06F9/26

CPC classification number: G06F13/4036

Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Abstract translation: 桥接总线桥内的多个总线的方法可以包括确定总线桥的队列是否包括指向受限地址范围的事务请求，并且对于每个接收的事务请求，确定事务请求的地址是否为 指示在受限地址范围内。 可以根据交易请求所针对的地址是否在受限地址范围内以及该队列是否包括指向受限地址范围的交易请求，来选择性地拒绝总线桥接器接收的每个交易请求。

公开(公告)号：US07269805B1

公开(公告)日：2007-09-11

申请号：US10836995

申请日：2004-04-30

Applicant: Ahmad R. Ansari ,  Mehul R. Vashi ,  Nigel G. Herron ,  Stephen M. Douglass

Inventor： Ahmad R. Ansari ,  Mehul R. Vashi ,  Nigel G. Herron ,  Stephen M. Douglass

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F11/27

Abstract: Method and apparatus for generating a test program for an integrated circuit having an embedded processor. One embodiment has a system which includes an embedded microprocessor; a plurality of assembly language instructions stored in a memory, where the assembly language instructions substantially exercise a critical path or a path closest to the critical path in the embedded microprocessor; and programmable test circuitry having a programmable clock circuit for providing a multiplied clock signal to the embedded microprocessor in order to execute the assembly language instructions.

Abstract translation: 用于生成具有嵌入式处理器的集成电路的测试程序的方法和装置。 一个实施例具有包括嵌入式微处理器的系统; 存储在存储器中的多个汇编语言指令，其中所述汇编语言指令基本上行使关键路径或最接近所述嵌入式微处理器中的关键路径的路径; 以及具有可编程时钟电路的可编程测试电路，用于向嵌入式微处理器提供倍增时钟信号，以执行汇编语言指令。