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    Programmable logic device with hierarchical confiquration and state storage
    11.
    发明授权
    Programmable logic device with hierarchical confiquration and state storage 失效
    具有分层配置和状态存储的可编程逻辑器件

    公开(公告)号：US5778439A

    公开(公告)日：1998-07-07

    申请号：US517019

    申请日：1995-08-18

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    IPC分类号： H03K19/177 ,  G06F12/02

    CPC分类号： H03K19/17776 ,  H03K19/17748 ,  H03K19/17752 ,  H03K19/1776

    摘要： In accordance with the present invention, a programmable array includes hierarchical configuration and state storage. The array comprises an active storage for an active configuration and an active state as well as an inactive storage for one or more inactive configurations and one or more inactive states. The array further comprises logic and routing configured by the active configuration. The logic includes a plurality of combinational elements and a plurality of sequential logic elements for providing the states. Bits are transferred between the active and the inactive storage. The inactive storage is accessible for read or write operations by the active configuration by a structure comprising: a core including a plurality of configurable elements selectively coupled to each other, a memory controller for controlling the memory that configures the logic and routing in accordance with the active configuration, a command register to hold commands for the memory controller, a memory address register to address the memory, and a memory data register coupled to the memory and the plurality of combinational elements. In one embodiment, the array of the present invention includes a configurable routing structure for providing the active configuration access to the memory address register, the memory data register, and the command register. The configurable routing structure is generally controlled by signals from the user logic, thereby significantly increasing user flexibility in using the programmable array.

    摘要翻译： 根据本发明，可编程阵列包括分层配置和状态存储。 阵列包括用于活动配置和活动状态的活动存储器以及用于一个或多个非活动配置和一个或多个非活动状态的非活动存储器。 该阵列还包括由活动配置配置的逻辑和路由。 逻辑包括多个组合元件和用于提供状态的多个顺序逻辑元件。 位在活动和非活动存储之间传输。 非活动存储器可由活动配置通过以下结构进行读取或写入操作：包括：选择性地彼此耦合的多个可配置元件的核心;存储器控制器，用于根据所述存储器控制配置逻辑和路由 活动配置，用于保存用于存储器控制器的命令的命令寄存器，用于寻址存储器的存储器地址寄存器以及耦合到存储器和多个组合元件的存储器数据寄存器。 在一个实施例中，本发明的阵列包括用于提供对存储器地址寄存器，存储器数据寄存器和命令寄存器的有效配置访问的可配置路由结构。 可配置路由结构通常由来自用户逻辑的信号控制，从而显着增加用户使用可编程阵列的灵活性。

    Configuration modes for a time multiplexed programmable logic device
    12.
    发明授权
    Configuration modes for a time multiplexed programmable logic device 失效
    时间复用可编程逻辑器件的配置模式

    公开(公告)号：US5600263A

    公开(公告)日：1997-02-04

    申请号：US517018

    申请日：1995-08-18

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert A. Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert A. Johnson ,  Jennifer Wong

    IPC分类号： G06F15/78 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1737 ,  G06F15/7867 ,  G06F17/5054

    摘要： A PLD is operable in a variety of modes. In a first mode, the timeshare mode, the PLD remains at a single configuration for a plurality of user clock cycles. In a second mode, the logic engine mode, the PLD sequences through multiple configurations for each user cycle. In this mode, the period of time during which a configuration is active is called a micro cycle. In a third mode, the static mode, multiple configurations are programmed identically, so that the PLD performs the same function regardless of the configuration. Finally, the PLD is also operable in a combination mode, wherein part of the chip operates in one mode, for example, the static mode, and another part of the chip operates in the logic engine mode or the timeshare mode. In an alternative or co-existing embodiment, the PLD operates in one configuration mode during at least one user cycle and in another configuration mode during at least another user cycle.

    摘要翻译： PLD可以以各种模式操作。 在第一模式中，分时共享模式，对于多个用户时钟周期，PLD保持在单个配置。 在第二种模式下，逻辑引擎模式，PLD序列通过多个配置为每个用户周期。 在该模式中，配置有效的时间段称为微循环。 在第三种模式下，静态模式，多个配置被编程相同，以便PLD执行相同的功能，无论配置如何。 最后，PLD还可以以组合模式工作，其中芯片的一部分以一种模式工作，例如静态模式，芯片的另一部分以逻辑引擎模式或分时模式运行。 在备选或共存的实施例中，PLD在至少一个用户周期期间以及在至少另一个用户周期的另一配置模式下以一种配置模式运行。

    Sequencer for a time multiplexed programmable logic device
    13.
    发明授权
    Sequencer for a time multiplexed programmable logic device 失效
    时序复用可编程逻辑器件的序列发生器

    公开(公告)号：US5583450A

    公开(公告)日：1996-12-10

    申请号：US517020

    申请日：1995-08-18

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert A. Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert A. Johnson ,  Jennifer Wong

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17752 ,  H03K19/17704

    摘要： A programmable logic device (PLD) includes at least one configurable element, a plurality of programmable logic elements for configuring the configurable element(s), and a sequencer coupled to the plurality of programmable logic elements. Each programmable logic element typically includes a plurality of memory cells, wherein the sequencer accesses one of the plurality of memory cells during one step in a sequence of steps, each step initiated by one or more trigger signals. If the sequencer receives a plurality of trigger signals simultaneously, then the sequencer prioritizes these signals. Generally, each step provides one configuration of the PLD. In one embodiment, the sequence of steps includes less than all configurations of the PLD. In another embodiment, one trigger signal initiates a plurality of sequences of configurations.

    摘要翻译： 可编程逻辑器件（PLD）包括至少一个可配置元件，用于配置可配置元件的多个可编程逻辑元件，以及耦合到多个可编程逻辑元件的定序器。 每个可编程逻辑元件通常包括多个存储器单元，其中定序器在一个步骤中的一个步骤中访问多个存储器单元之一，每个步骤由一个或多个触发信号启动。 如果定序器同时接收多个触发信号，则定序器对这些信号进行优先级排序。 通常，每个步骤提供PLD的一个配置。 在一个实施例中，步骤序列包括少于PLD的所有配置。 在另一个实施例中，一个触发信号启动多个配置序列。

    Method of time multiplexing a programmable logic device
    14.
    发明授权
    Method of time multiplexing a programmable logic device 有权
    时间复用可编程逻辑器件的方法

    公开(公告)号：US06263430B1

    公开(公告)日：2001-07-17

    申请号：US09363940

    申请日：1999-07-29

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    IPC分类号： G06F900

    CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/1776

    摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

    摘要翻译： 可编程逻辑器件（PLD）包括至少一个可配置元件和用于配置可配置元件的多个可编程逻辑元件。 或者，PLD包括用于配置互连结构的互连结构和多个可编程逻辑元件。 在任一实施例中，至少一个可编程逻辑元件包括N个存储器单元。 N个存储器单元中的预定的一个形成存储器片的一部分，其中可编程逻辑器件的每个片的至少一部分被分配给配置数据或用户数据存储器。 通常，一个存储器片提供可编程逻辑器件的一个配置。 根据一个实施例，存储器访问端口耦合在N个存储器单元中的至少一个和任一个可配置元件或互连之间，从而有助于在一个配置期间将新的配置数据加载到其他存储器片段中。 新的配置数据可以包括片外或片上数据。 本发明通常将至少一个片分配给用户数据存储器，并且包括用于禁止对N个存储器单元中的至少一个的访问的装置。

    Programmable logic device including configuration data or user data memory slices
    15.
    发明授权
    Programmable logic device including configuration data or user data memory slices 失效
    可编程逻辑器件包括配置数据或用户数据存储器片

    公开(公告)号：US5959881A

    公开(公告)日：1999-09-28

    申请号：US1156

    申请日：1997-12-30

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    IPC分类号： G06F17/50 ,  G11C5/00 ,  H03K19/177 ,  G11C13/00

    CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/1776

    摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

    摘要翻译： 可编程逻辑器件（PLD）包括至少一个可配置元件和用于配置可配置元件的多个可编程逻辑元件。 或者，PLD包括用于配置互连结构的互连结构和多个可编程逻辑元件。 在任一实施例中，至少一个可编程逻辑元件包括N个存储器单元。 N个存储器单元中的预定的一个形成存储器片的一部分，其中可编程逻辑器件的每个片的至少一部分被分配给配置数据或用户数据存储器。 通常，一个存储器片提供可编程逻辑器件的一个配置。 根据一个实施例，存储器访问端口耦合在N个存储器单元中的至少一个和任一个可配置元件或互连之间，从而有助于在一个配置期间将新的配置数据加载到其他存储器片段中。 新的配置数据可以包括片外或片上数据。 本发明通常将至少一个片分配给用户数据存储器，并且包括用于禁止对N个存储器单元中的至少一个的访问的装置。

    Time multiplexed programmable logic device
    16.
    发明授权
    Time multiplexed programmable logic device 失效
    时分复用可编程逻辑器件

    公开(公告)号：US5646545A

    公开(公告)日：1997-07-08

    申请号：US516186

    申请日：1995-08-18

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    IPC分类号： G11C11/401 ,  G06F15/78 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1776 ,  G06F15/7867 ,  G06F17/5054 ,  H03K19/17704

    摘要： A programmable logic device (PLD) comprises a plurality of configurable logic blocks (CLBs), an interconnect structure for interconnecting the CLBs, and a plurality of programmable logic elements for configuring the CLBs and the interconnect structure. Each CLB includes a combinational element and a sequential logic element, wherein at least one programmable logic element includes a plurality of memory cells for configuring the combinational element and at least one programmable logic element includes a plurality of memory cells for configuring the sequential logic element. A micro register, which stores a plurality of intermediate states of one CLB or interconnect structure, is located at the output of a CLB, the input of a CLB, or elsewhere in the interconnect structure. The PLD includes means for disabling access to at least one of said plurality of memory elements. In one embodiment, the memory cells are RAM cells, whereas in other embodiments the memory cells are ROM cells, or a combination thereof. The PLD switches between configurations sequentially, by random access, or on command from an external or internal signal. This reconfiguration allows the PLD to function in one of N configurations, wherein N is equal to the maximum number of memory cells assigned to each programmable point. In this manner, a PLD with a number M of actual CLBs functions as if it includes M times N effective CLBs.

    摘要翻译： 可编程逻辑器件（PLD）包括多个可配置逻辑块（CLB），用于互连CLB的互连结构以及用于配置CLB和互连结构的多个可编程逻辑元件。 每个CLB包括组合元件和顺序逻辑元件，其中至少一个可编程逻辑元件包括用于配置组合元件的多个存储器单元，并且至少一个可编程逻辑元件包括用于配置顺序逻辑元件的多个存储器单元。 存储一个CLB或互连结构的多个中间状态的微寄存器位于CLB的输出端，CLB的输入端或互连结构中的别处。 PLD包括用于禁止访问所述多个存储器元件中的至少一个的装置。 在一个实施例中，存储器单元是RAM单元，而在其他实施例中，存储器单元是ROM单元或其组合。 PLD通过随机访问或从外部或内部信号的命令顺序地在配置之间切换。 这种重新配置允许PLD以N种配置之一工作，其中N等于分配给每个可编程点的最大存储器单元数。 以这种方式，具有M个实际CLB的PLD的功能就好像它包括M次N个有效CLB。

    Digital clock manager having cascade voltage switch logic clock paths
    17.
    发明授权
    Digital clock manager having cascade voltage switch logic clock paths 有权
    数字时钟管理器具有级联电压开关逻辑时钟路径

    公开(公告)号：US07038519B1

    公开(公告)日：2006-05-02

    申请号：US10837324

    申请日：2004-04-30

    申请人： Raymond C. Pang ,  Jennifer Wong

    发明人： Raymond C. Pang ,  Jennifer Wong

    IPC分类号： H03H11/26

    CPC分类号： H03K19/1738 ,  H03H11/26 ,  H03K2005/00195 ,  H03K2005/00228 ,  H03K2005/00234

    摘要： A digital clock manager having differential clock signal paths is provided. The differential clock signal paths are provided by replacing single-ended circuit elements of a conventional digital clock manager with symmetrical cascade voltage switch logic (CVSL) circuit elements, including CVSL delay buffers, CVSL multiplexers, CVSL AND gates, CVSL OR gates and CVSL set-reset latches. These symmetrical CVSL AND gates, CVSL OR gates and CVSL set-reset latches represent new circuit elements.

    摘要翻译： 提供具有差分时钟信号路径的数字时钟管理器。 差分时钟信号路径通过用传统数字时钟管理器的单端电路元件替代对称级联电压开关逻辑（CVSL）电路元件来提供，包括CVSL延迟缓冲器，CVSL多路复用器，CVSL与门，CVSL或门和CVSL组 - 锁存器。 这些对称的CVSL与门，CVSL或门和CVSL设置复位锁存器代表新的电路元件。