利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

26 条记录 (耗时 0.025 秒)

    Methods and Systems to Facilitate Operation in Unpinned Memory
    11.
    发明申请
    Methods and Systems to Facilitate Operation in Unpinned Memory 有权
    方法和系统促进无内存操作

    公开(公告)号：US20130147821A1

    公开(公告)日：2013-06-13

    申请号：US13324443

    申请日：2011-12-13

    申请人： Warren Fritz Kruger ,  Philip J. Rogers ,  Mark Hummel

    发明人： Warren Fritz Kruger ,  Philip J. Rogers ,  Mark Hummel

    IPC分类号： G06F13/00 ,  G06F12/00

    CPC分类号： G06F12/08

    摘要： In an embodiment, a method of processing memory requests in a first processing device is provided. The method includes generating a memory request associated with a memory address located in an unpinned memory space managed by an operating system running on a second processing device; and responsive to a determination that the memory address is not resident in a physical memory, transmitting a message to the second processing device. In response to the message, the operating system controls the second processing device to bring the memory address into the physical memory.

    摘要翻译： 在一个实施例中，提供了一种在第一处理设备中处理存储器请求的方法。 该方法包括：产生与位于由在第二处理设备上运行的操作系统管理的未被固定的存储器空间中的存储器地址相关联的存储器请求; 并且响应于所述存储器地址不驻留在物理存储器中的确定，向第二处理设备发送消息。 响应于该消息，操作系统控制第二处理设备以使存储器地址进入物理存储器。

    Method and apparatus synchronizing integrated circuit clocks
    12.
    发明授权
    Method and apparatus synchronizing integrated circuit clocks 有权
    方法和装置同步集成电路时钟

    公开(公告)号：US08443225B2

    公开(公告)日：2013-05-14

    申请号：US13584560

    申请日：2012-08-13

    申请人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    发明人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    IPC分类号： G06F1/12

    CPC分类号： G11C7/1045

    摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

    摘要翻译： 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

    METHOD AND APPARATUS SYNCHRONIZING INTEGRATED CIRCUIT CLOCKS
    13.
    发明申请
    METHOD AND APPARATUS SYNCHRONIZING INTEGRATED CIRCUIT CLOCKS 有权
    方法和装置同步集成电路时钟

    公开(公告)号：US20120303995A1

    公开(公告)日：2012-11-29

    申请号：US13584560

    申请日：2012-08-13

    申请人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    发明人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    IPC分类号： G06F1/12 ,  G06F1/04

    CPC分类号： G11C7/1045

    摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

    摘要翻译： 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

    Method and Apparatus Synchronizing Integrated Circuit Clocks
    15.
    发明申请
    Method and Apparatus Synchronizing Integrated Circuit Clocks 有权
    同步集成电路时钟的方法和装置

    公开(公告)号：US20110019787A1

    公开(公告)日：2011-01-27

    申请号：US12509409

    申请日：2009-07-24

    申请人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    发明人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    IPC分类号： H04L7/00 ,  H03K19/096

    CPC分类号： G11C7/1045

    摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

    摘要翻译： 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以便进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

    Methods and systems to facilitate operation in unpinned memory
    16.
    发明授权
    Methods and systems to facilitate operation in unpinned memory 有权
    方便和系统，以方便在无内存中的操作

    公开(公告)号：US08842126B2

    公开(公告)日：2014-09-23

    申请号：US13324443

    申请日：2011-12-13

    申请人： Warren Fritz Kruger ,  Philip J. Rogers ,  Mark Hummel

    发明人： Warren Fritz Kruger ,  Philip J. Rogers ,  Mark Hummel

    IPC分类号： G06F13/00 ,  G06F13/28

    CPC分类号： G06F12/08

    摘要： In an embodiment, a method of processing memory requests in a first processing device is provided. The method includes generating a memory request associated with a memory address located in an unpinned memory space managed by an operating system running on a second processing device; and responsive to a determination that the memory address is not resident in a physical memory, transmitting a message to the second processing device. In response to the message, the operating system controls the second processing device to bring the memory address into the physical memory.

    摘要翻译： 在一个实施例中，提供了一种在第一处理设备中处理存储器请求的方法。 该方法包括：产生与位于由在第二处理设备上运行的操作系统管理的未被固定的存储器空间中的存储器地址相关联的存储器请求; 并且响应于所述存储器地址不驻留在物理存储器中的确定，向第二处理设备发送消息。 响应于该消息，操作系统控制第二处理设备以使存储器地址进入物理存储器。

    METHOD AND SYSTEM FOR FRAME BUFFER PROTECTION
    17.
    发明申请
    METHOD AND SYSTEM FOR FRAME BUFFER PROTECTION 审中-公开
    框架缓冲保护方法与系统

    公开(公告)号：US20130166922A1

    公开(公告)日：2013-06-27

    申请号：US13599609

    申请日：2012-08-30

    申请人： Daniel W. Wong ,  Warren Fritz Kruger ,  David I.J. Glen ,  Gongxian J. Cheng

    发明人： Daniel W. Wong ,  Warren Fritz Kruger ,  David I.J. Glen ,  Gongxian J. Cheng

    IPC分类号： G06F12/14

    CPC分类号： G06F21/10 ,  G06F12/1416 ,  G06F21/84

    摘要： When content, such as premium video or audio, is decoded, the content is stored in protected memory segments. Read access to the protected memory segments from a component not in a frame buffer protected (FBP) mode is blocked by a memory controller. The memory controller also blocks components in the FBP mode from writing to unprotected memory segments. The content may be processed by a processing engine operating in the FBP mode and may only be written back to protected memory segments. The memory segment may later be marked as unprotected if the memory segment is no longer needed. If the content is encrypted in protected memory, the encrypting key associated with the memory segment may be removed. If the content is stored in the clear, the protected memory segments are scrubbed before releasing the segments for use as unprotected memory segments.

    摘要翻译： 当诸如高级视频或音频的内容被解码时，内容被存储在受保护的存储器段中。 从不在帧缓冲区保护（FBP）模式的组件读取受保护的存储器段的访问被存储器控制器阻止。 存储器控制器还阻止FBP模式中的组件写入不受保护的存储器段。 内容可以由在FBP模式下操作的处理引擎来处理，并且可以仅被写回到受保护的存储器段。 如果不再需要存储器段，则存储器段可以稍后被标记为不受保护。 如果内容在受保护的存储器中被加密，则可以去除与存储器段相关联的加密密钥。 如果内容以清晰的方式存储，则在释放用作无保护内存段的段之前，将对受保护的内存段进行擦除。

    Adjustment of Write Timing Based on Error Detection Techniques
    18.
    发明申请
    Adjustment of Write Timing Based on Error Detection Techniques 有权
    基于错误检测技术调整写入时序

    公开(公告)号：US20110185256A1

    公开(公告)日：2011-07-28

    申请号：US12846958

    申请日：2010-07-30

    申请人： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

    发明人： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

    IPC分类号： G06F11/08

    CPC分类号： G06F13/4243

    摘要： A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

    摘要翻译： 提供了一种方法，系统和计算机程序产品，用于基于错误检测功能的结果来调整存储器件中的写入定时。 例如，该方法可以包括基于错误检测功能的结果来确定数据总线上的信号与写入时钟信号之间的写时序窗口。 该方法还可以包括基于写时序窗口来调整数据总线上的信号与写入时钟信号之间的相位差。 存储器件可以基于调整后的相位差来恢复数据总线上的数据。