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    Method and apparatus synchronizing integrated circuit clocks
    2.
    发明授权
    Method and apparatus synchronizing integrated circuit clocks 有权
    方法和装置同步集成电路时钟

    公开(公告)号：US08245073B2

    公开(公告)日：2012-08-14

    申请号：US12509409

    申请日：2009-07-24

    申请人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    发明人： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

    IPC分类号： G06F1/12

    CPC分类号： G11C7/1045

    摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

    摘要翻译： 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

    CIRCUIT AND METHOD TO CONTROL SLEW RATE OF A CURRENT-MODE LOGIC OUTPUT DRIVER
    5.
    发明申请
    CIRCUIT AND METHOD TO CONTROL SLEW RATE OF A CURRENT-MODE LOGIC OUTPUT DRIVER 有权
    用于控制电流模式逻辑输出驱动器的电流的电路和方法

    公开(公告)号：US20120299616A1

    公开(公告)日：2012-11-29

    申请号：US13114479

    申请日：2011-05-24

    申请人： Xin Liu ,  Arvind Bomdica ,  Ming-Ju Edward Lee

    发明人： Xin Liu ,  Arvind Bomdica ,  Ming-Ju Edward Lee

    IPC分类号： H03K5/01

    CPC分类号： H03K5/01 ,  H04L25/0272 ,  H04L25/0282

    摘要： A method is provided for selecting at least one of a plurality of slew rate control settings based at least upon a speed of data transmission and receiving input data where the input data is received at the data transmission speed. The method also includes switching the received input data in accordance with the selected at least one of a plurality of slew rate control settings and sending output data at the data transmission speed. Also provided is data driver device that includes at least one activation portion comprising one or more slew rate controls, a voltage-mode driver portion and at least a first current-mode driver portion. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the data driver device. Also provided is a system including the data driver device, a data storage device and a processor device.

    摘要翻译： 提供了一种至少根据数据传输的速度选择多个转换速率控制设置中的至少一个并接收以数据传输速度接收输入数据的输入数据的方法。 该方法还包括根据所选择的多个转换速率控制设置中的至少一个切换所接收的输入数据，并以数据传输速度发送输出数据。 还提供了数据驱动器装置，其包括至少一个包括一个或多个转换速率控制的激活部分，电压模式驱动器部分和至少第一电流模式驱动器部分。 还提供了一种用数据编码的计算机可读存储设备，用于使制造设施适配以创建数据驱动器设备。 还提供了包括数据驱动器装置，数据存储装置和处理器装置的系统。

    Electrostatic discharge power clamp trigger circuit using low stress voltage devices
    6.
    发明授权
    Electrostatic discharge power clamp trigger circuit using low stress voltage devices 有权
    静电放电电源钳位触发电路采用低应力电压器件

    公开(公告)号：US08102632B2

    公开(公告)日：2012-01-24

    申请号：US12406684

    申请日：2009-03-18

    申请人： Yikai Liang ,  Arvind Bomdica ,  Samudyatha Suryanarayana ,  Gayatri Gopalan ,  Min Xu ,  Xin Liu ,  Ming-Ju Edward Lee

    发明人： Yikai Liang ,  Arvind Bomdica ,  Samudyatha Suryanarayana ,  Gayatri Gopalan ,  Min Xu ,  Xin Liu ,  Ming-Ju Edward Lee

    IPC分类号： H02H9/00 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06

    CPC分类号： H03K19/00315

    摘要： Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.

    摘要翻译： 描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。 位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路，以保护IC免受过多的电源电压和ESD电压的影响。 每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。 实施例的保护电路包括高电压IO引脚接口，耦合到IO引脚的电压降网络，并且包括串联连接的多个正向偏置二极管以将IO引脚上的高电压降低到低电压电平， 耦合在所述电压降网络和接地端子之间的NMOS分流晶体管，以及耦合到所述NMOS分流晶体管的触发电路，以在感测到的输入电压上升时间短于限定的电源电压上升时间时激活所述并联晶体管。

    Adjustment of Write Timing Based on Error Detection Techniques
    7.
    发明申请
    Adjustment of Write Timing Based on Error Detection Techniques 有权
    基于错误检测技术调整写入时序

    公开(公告)号：US20110185256A1

    公开(公告)日：2011-07-28

    申请号：US12846958

    申请日：2010-07-30

    申请人： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

    发明人： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

    IPC分类号： G06F11/08

    CPC分类号： G06F13/4243

    摘要： A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

    摘要翻译： 提供了一种方法，系统和计算机程序产品，用于基于错误检测功能的结果来调整存储器件中的写入定时。 例如，该方法可以包括基于错误检测功能的结果来确定数据总线上的信号与写入时钟信号之间的写时序窗口。 该方法还可以包括基于写时序窗口来调整数据总线上的信号与写入时钟信号之间的相位差。 存储器件可以基于调整后的相位差来恢复数据总线上的数据。

    Electrostatic Discharge Power Clamp Trigger Circuit Using Low Stress Voltage Devices
    9.
    发明申请
    Electrostatic Discharge Power Clamp Trigger Circuit Using Low Stress Voltage Devices 有权
    使用低应力电压器件的静电放电电源钳位触发电路

    公开(公告)号：US20100238598A1

    公开(公告)日：2010-09-23

    申请号：US12406684

    申请日：2009-03-18

    申请人： Yikai Liang ,  Arvind Bomdica ,  Samudyatha Suryanarayana ,  Gayatri Gopalan ,  Min Xu ,  Xin Liu ,  Ming-Ju Edward Lee

    发明人： Yikai Liang ,  Arvind Bomdica ,  Samudyatha Suryanarayana ,  Gayatri Gopalan ,  Min Xu ,  Xin Liu ,  Ming-Ju Edward Lee

    IPC分类号： H02H9/04 ,  G06F17/00

    CPC分类号： H03K19/00315

    摘要： Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.

    摘要翻译： 描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。 位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路，以保护IC免受过多的电源电压和ESD电压的影响。 每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。 实施例的保护电路包括高电压IO引脚接口，耦合到IO引脚的电压降网络，并且包括串联连接的多个正向偏置二极管以将IO引脚上的高电压降低到低电压电平， 耦合在所述电压降网络和接地端子之间的NMOS分流晶体管，以及耦合到所述NMOS分流晶体管的触发电路，以在感测到的输入电压上升时间短于限定的电源电压上升时间时激活所述并联晶体管。

    Bias circuit for a complementary current mode logic drive circuit
    10.
    发明授权
    Bias circuit for a complementary current mode logic drive circuit 有权
    用于互补电流模式逻辑驱动电路的偏置电路

    公开(公告)号：US08564583B2

    公开(公告)日：2013-10-22

    申请号：US12640180

    申请日：2009-12-17

    申请人： Kevin Yikai Liang ,  Xin Liu ,  Arvind Bomdica ,  Ming-Ju Edward Lee

    发明人： Kevin Yikai Liang ,  Xin Liu ,  Arvind Bomdica ,  Ming-Ju Edward Lee

    IPC分类号： G06F3/038

    CPC分类号： H03K19/018514 ,  H03K19/018528

    摘要： A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage.

    摘要翻译： 电路包括互补电流模式逻辑驱动器电路和双反馈电流模式逻辑偏置电路。 互补电流模式逻辑驱动器电路提供第一输出电压和第二输出电压。 双反馈电流模式逻辑偏置电路包括第一反馈电路和第二反馈电路。 第一反馈电路响应于第一输出电压为互补电流模式逻辑驱动器电路提供第一偏置电压。 第二反馈电路响应于第二输出电压提供第二偏置电压。