公开(公告)号：US5541132A

公开(公告)日：1996-07-30

申请号：US408653

申请日：1995-03-21

申请人： Robert B. Davies ,  Vida Ilderem ,  Mark D. Griswold ,  Diann Dow ,  James E. Prendergast ,  Iksung Lim ,  Juan Buxo ,  Richard D. Sivan ,  James D. Burnett ,  Frank K. Baker

发明人： Robert B. Davies ,  Vida Ilderem ,  Mark D. Griswold ,  Diann Dow ,  James E. Prendergast ,  Iksung Lim ,  Juan Buxo ,  Richard D. Sivan ,  James D. Burnett ,  Frank K. Baker

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423 ,  H01L21/265

CPC分类号： H01L29/66659 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/42368 ,  Y10S438/981

摘要： An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).

摘要翻译： 具有减小的栅极 - 漏极电容的绝缘栅场效应晶体管（10）和制造场效应晶体管（10）的方法。 掺杂剂阱（13）形成在半导体材料（11）中。 栅极氧化物层（26）形成在掺杂剂阱（13）上，其中栅极氧化物层（26）和具有栅极接触部分（43）和栅极延伸部分（44）的栅极结构（41）。 栅极接触部分（43）允许与栅极结构（41）的电接触，而栅极延伸部分（44）用作有源栅极部分。 与栅极接触部分（43）相邻的栅极氧化物（26）的一部分被加厚以降低场效应晶体管（10）的栅极到漏极电容，从而增加绝缘栅极场效应晶体管（10）的带宽。

公开(公告)号：US5101257A

公开(公告)日：1992-03-31

申请号：US724285

申请日：1991-07-01

申请人： James D. Hayden ,  Thomas C. Mele ,  Frank K. Baker

发明人： James D. Hayden ,  Thomas C. Mele ,  Frank K. Baker

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H01L27/07

CPC分类号： G11C13/003 ,  H01L27/0716 ,  G11C2213/74

摘要： A semiconductor device (10) has a bipolar transistor merged with an MOS transistor, the two transistors being separated essentially by a sidewall spacer and the bipolar transistor being self-aligned to the MOS transistor. The MOS transistor includes a gate (22) and a sorce region (38). A drain region of the MOS transistor is also an active base region (27) of the bipolar transistor. The bipoloar transistor further includes a first emitter region (40) formed in the active base region and a second emitter region (32) which is formed on the first emitter region and partially overlies the MOS transistor gate. The second emitter region is separated from the gate by a sidewall spacer (29) and an overlying dielectric layer (23).

公开(公告)号：US5243203A

公开(公告)日：1993-09-07

申请号：US787155

申请日：1991-11-04

申请人： James D. Hayden ,  Frank K. Baker

发明人： James D. Hayden ,  Frank K. Baker

IPC分类号： H01L27/11

CPC分类号： H01L27/1108 ,  Y10S257/903

摘要： A pair of first and second thin film transistors (TFTs). The transistors are formed from a first continuous, conductive region (38) and a second continuous, conductive region (39) which underlies the first conductive region (38). The first transistor has a source region (50), a drain region (54), and a channel region (52) created from three distinct and separate regions of conductor region (39). The first transistor has a gate region (53) that overlies the channel region (52). The gate region (53) is formed from a distinct region of conductive region (38). The second transistor has a source region (44), a drain region (48), and a channel region (46) which are created from three distinct and separate regions of conductor region (38). The second transistor has a gate region (47) that underlies the channel region (46). The gate region (47) is formed from a distinct region of conductive region (39).

摘要翻译： 一对第一和第二薄膜晶体管（TFT）。 晶体管由位于第一导电区域（38）下方的第一连续导电区域（38）和第二连续导电区域（39）形成。 第一晶体管具有源极区域（50），漏极区域（54）和由导体区域（39）的三个不同且分离的区域形成的沟道区域（52）。 第一晶体管具有覆盖沟道区（52）的栅极区（53）。 栅极区域（53）由导电区域（38）的不同区域形成。 第二晶体管具有由导体区域（38）的三个不同且分离的区域产生的源极区（44），漏极区（48）和沟道区（46）。 第二晶体管具有在沟道区（46）下面的栅极区（47）。 栅极区域（47）由导电区域（39）的不同区域形成。

公开(公告)号：US5024971A

公开(公告)日：1991-06-18

申请号：US570180

申请日：1990-08-20

申请人： Frank K. Baker ,  James D. Hayden

发明人： Frank K. Baker ,  James D. Hayden

IPC分类号： H01L21/308

CPC分类号： H01L21/3081 ,  H01L21/3086 ,  Y10S148/105 ,  Y10S148/147 ,  Y10S438/945 ,  Y10S438/947

摘要： The invention provides a method for patterning a submicron opening in a layer of semiconductor material. The method comprises use of conventional photolithography to position a sidewall spacer in a predetermined location on a semiconductor device. A layer of cobalt is selectively reacted with an underlying layer to form an image reversal layer which functions as a hard mask. The submicron features are then transferred into the underlying layer of semiconducting material by etching.

摘要翻译： 本发明提供了一种在半导体材料层中图形化亚微米开口的方法。 该方法包括使用常规光刻法将侧壁间隔物定位在半导体器件上的预定位置。 一层钴选择性地与下层反应以形成用作硬掩模的图像反转层。 然后通过蚀刻将亚微米特征转移到半导体材料的下层中。

公开(公告)号：US5485420A

公开(公告)日：1996-01-16

申请号：US278465

申请日：1994-07-21

申请人： Craig S. Lage ,  Frank K. Baker ,  James D. Hayden ,  Kent J. Cooper

发明人： Craig S. Lage ,  Frank K. Baker ,  James D. Hayden ,  Kent J. Cooper

IPC分类号： G11C11/412 ,  H01L21/8244 ,  G11C11/00

CPC分类号： H01L27/11 ,  G11C11/412 ,  Y10S257/903

摘要： The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

摘要翻译： 本发明包括具有与衬底内的区域接触的自对准接触的集成电路和与掺杂区相邻的电容器的电容器板。 本发明还包括具有第一板和第二板的电容器的静态随机存取存储单元。 第一板包括晶体管的栅电极的第一板部分，第二板包括与第一板部分基本一致的第一导电部件。 第二板可以形成在锁存晶体管的栅电极上或字线之上。 本公开包括形成集成电路和静态随机存取存储器单元的方法。

公开(公告)号：US5377139A

公开(公告)日：1994-12-27

申请号：US990341

申请日：1992-12-11

申请人： Craig S. Lage ,  Frank K. Baker ,  James D. Hayden ,  Kent J. Cooper

发明人： Craig S. Lage ,  Frank K. Baker ,  James D. Hayden ,  Kent J. Cooper

IPC分类号： G11C11/412 ,  H01L21/8244 ,  G11C13/00

CPC分类号： H01L27/11 ,  G11C11/412 ,  Y10S257/903

摘要： The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

摘要翻译： 本发明包括具有与衬底内的区域接触的自对准接触的集成电路和与掺杂区相邻的电容器的电容器板。 本发明还包括具有第一板和第二板的电容器的静态随机存取存储单元。 第一板包括晶体管的栅电极的第一板部分，第二板包括与第一板部分基本一致的第一导电部件。 第二板可以形成在锁存晶体管的栅电极上或字线之上。 本公开包括形成集成电路和静态随机存取存储器单元的方法。

公开(公告)号：US4801555A

公开(公告)日：1989-01-31

申请号：US3176

申请日：1987-01-14

申请人： Patrick J. Holly ,  Louis C. Parrillo ,  Frank K. Baker

发明人： Patrick J. Holly ,  Louis C. Parrillo ,  Frank K. Baker

IPC分类号： H01L21/265

CPC分类号： H01L21/26513 ,  Y10S148/082 ,  Y10S148/083

摘要： A process for forming graded source/drain regions in semiconductor devices involves two ion implantation steps and an optional drive-in step. The first implantation is a low dose implant with high energy and/or low mass ions to form the deeper grading region. The second implant is a high does implant with low energy and/or high mass ions to form the shallower, lower resistivity source/drain region. Without the optional drive-in step, virtually no lateral grading takes place, resulting in little encroachment of the grading region under the gate. The use of a drive-in step between the two implant steps causes diffusion of the grading dopant, which increases the grading both laterally and vertically, resulting in better breakdown and capacitance characteristics, but increased encroachment under the gate. The present invention allows control over the lateral and vertical grading separately to optimize the trade-offs for a particular application.

摘要翻译： 用于在半导体器件中形成分级源极/漏极区域的方法包括两个离子注入步骤和可选的驱入步骤。 第一次植入是具有高能量和/或低质量离子的低剂量植入物以形成较深的分级区域。 第二种植入物是具有低能量和/或高质量离子的植入物，以形成较浅的较低电阻率源极/漏极区域。 没有可选的驱动步骤，几乎没有发生横向分级，导致栅极下方的分级区域几乎不受侵蚀。 在两个植入步骤之间的驱动步骤的使用导致分级掺杂剂的扩散，这增加了横向和垂直的分级，导致更好的击穿和电容特性，但增加了栅极下的侵蚀。 本发明允许单独控制横向和垂直分级以优化特定应用的权衡。