公开(公告)号：US5275964A

公开(公告)日：1994-01-04

申请号：US64994

申请日：1993-05-24

申请人： James D. Hayden ,  Frank K. Baker

发明人： James D. Hayden ,  Frank K. Baker

IPC分类号： H01L27/11 ,  H01L21/70

CPC分类号： H01L27/1108 ,  Y10S257/903

摘要： A pair of first and second thin film transistors (TFTs). The transistors are formed from a first continuous, conductive region (38) and a second continuous, conductive region (39) which underlies the first conductive region (38). The first transistor has a source region (50), a drain region (54), and a channel region (52) created from three distinct and separate regions of conductor region (39). The first transistor has a gate region (53) that overlies the channel region (52). The gate region (53) is formed from a distinct region of conductive region (38). The second transistor has a source region (44), a drain region (48), and a channel region (46) which are created from three distinct and separate regions of conductor region (38). The second transistor has a gate region (47) that underlies the channel region (46). The gate region (47) is formed from a distinct region of conductive region (39).

摘要翻译： 一对第一和第二薄膜晶体管（TFT）。 晶体管由位于第一导电区域（38）下方的第一连续导电区域（38）和第二连续导电区域（39）形成。 第一晶体管具有源极区域（50），漏极区域（54）和由导体区域（39）的三个不同且分离的区域形成的沟道区域（52）。 第一晶体管具有覆盖沟道区（52）的栅极区（53）。 栅极区域（53）由导电区域（38）的不同区域形成。 第二晶体管具有由导体区域（38）的三个不同且分离的区域产生的源极区（44），漏极区（48）和沟道区（46）。 第二晶体管具有在沟道区（46）下面的栅极区（47）。 栅极区域（47）由导电区域（39）的不同区域形成。

公开(公告)号：US5101257A

公开(公告)日：1992-03-31

申请号：US724285

申请日：1991-07-01

申请人： James D. Hayden ,  Thomas C. Mele ,  Frank K. Baker

发明人： James D. Hayden ,  Thomas C. Mele ,  Frank K. Baker

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H01L27/07

CPC分类号： G11C13/003 ,  H01L27/0716 ,  G11C2213/74

摘要： A semiconductor device (10) has a bipolar transistor merged with an MOS transistor, the two transistors being separated essentially by a sidewall spacer and the bipolar transistor being self-aligned to the MOS transistor. The MOS transistor includes a gate (22) and a sorce region (38). A drain region of the MOS transistor is also an active base region (27) of the bipolar transistor. The bipoloar transistor further includes a first emitter region (40) formed in the active base region and a second emitter region (32) which is formed on the first emitter region and partially overlies the MOS transistor gate. The second emitter region is separated from the gate by a sidewall spacer (29) and an overlying dielectric layer (23).

公开(公告)号：US5485420A

公开(公告)日：1996-01-16

申请号：US278465

申请日：1994-07-21

申请人： Craig S. Lage ,  Frank K. Baker ,  James D. Hayden ,  Kent J. Cooper

发明人： Craig S. Lage ,  Frank K. Baker ,  James D. Hayden ,  Kent J. Cooper

IPC分类号： G11C11/412 ,  H01L21/8244 ,  G11C11/00

CPC分类号： H01L27/11 ,  G11C11/412 ,  Y10S257/903

摘要： The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

摘要翻译： 本发明包括具有与衬底内的区域接触的自对准接触的集成电路和与掺杂区相邻的电容器的电容器板。 本发明还包括具有第一板和第二板的电容器的静态随机存取存储单元。 第一板包括晶体管的栅电极的第一板部分，第二板包括与第一板部分基本一致的第一导电部件。 第二板可以形成在锁存晶体管的栅电极上或字线之上。 本公开包括形成集成电路和静态随机存取存储器单元的方法。

公开(公告)号：US5377139A

公开(公告)日：1994-12-27

申请号：US990341

申请日：1992-12-11

申请人： Craig S. Lage ,  Frank K. Baker ,  James D. Hayden ,  Kent J. Cooper

发明人： Craig S. Lage ,  Frank K. Baker ,  James D. Hayden ,  Kent J. Cooper

IPC分类号： G11C11/412 ,  H01L21/8244 ,  G11C13/00

CPC分类号： H01L27/11 ,  G11C11/412 ,  Y10S257/903

摘要： The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.

摘要翻译： 本发明包括具有与衬底内的区域接触的自对准接触的集成电路和与掺杂区相邻的电容器的电容器板。 本发明还包括具有第一板和第二板的电容器的静态随机存取存储单元。 第一板包括晶体管的栅电极的第一板部分，第二板包括与第一板部分基本一致的第一导电部件。 第二板可以形成在锁存晶体管的栅电极上或字线之上。 本公开包括形成集成电路和静态随机存取存储器单元的方法。

公开(公告)号：US5243203A

公开(公告)日：1993-09-07

申请号：US787155

申请日：1991-11-04

申请人： James D. Hayden ,  Frank K. Baker

发明人： James D. Hayden ,  Frank K. Baker

IPC分类号： H01L27/11

CPC分类号： H01L27/1108 ,  Y10S257/903

摘要： A pair of first and second thin film transistors (TFTs). The transistors are formed from a first continuous, conductive region (38) and a second continuous, conductive region (39) which underlies the first conductive region (38). The first transistor has a source region (50), a drain region (54), and a channel region (52) created from three distinct and separate regions of conductor region (39). The first transistor has a gate region (53) that overlies the channel region (52). The gate region (53) is formed from a distinct region of conductive region (38). The second transistor has a source region (44), a drain region (48), and a channel region (46) which are created from three distinct and separate regions of conductor region (38). The second transistor has a gate region (47) that underlies the channel region (46). The gate region (47) is formed from a distinct region of conductive region (39).

摘要翻译： 一对第一和第二薄膜晶体管（TFT）。 晶体管由位于第一导电区域（38）下方的第一连续导电区域（38）和第二连续导电区域（39）形成。 第一晶体管具有源极区域（50），漏极区域（54）和由导体区域（39）的三个不同且分离的区域形成的沟道区域（52）。 第一晶体管具有覆盖沟道区（52）的栅极区（53）。 栅极区域（53）由导电区域（38）的不同区域形成。 第二晶体管具有由导体区域（38）的三个不同且分离的区域产生的源极区（44），漏极区（48）和沟道区（46）。 第二晶体管具有在沟道区（46）下面的栅极区（47）。 栅极区域（47）由导电区域（39）的不同区域形成。

公开(公告)号：US5024971A

公开(公告)日：1991-06-18

申请号：US570180

申请日：1990-08-20

申请人： Frank K. Baker ,  James D. Hayden

发明人： Frank K. Baker ,  James D. Hayden

IPC分类号： H01L21/308

CPC分类号： H01L21/3081 ,  H01L21/3086 ,  Y10S148/105 ,  Y10S148/147 ,  Y10S438/945 ,  Y10S438/947

摘要： The invention provides a method for patterning a submicron opening in a layer of semiconductor material. The method comprises use of conventional photolithography to position a sidewall spacer in a predetermined location on a semiconductor device. A layer of cobalt is selectively reacted with an underlying layer to form an image reversal layer which functions as a hard mask. The submicron features are then transferred into the underlying layer of semiconducting material by etching.

摘要翻译： 本发明提供了一种在半导体材料层中图形化亚微米开口的方法。 该方法包括使用常规光刻法将侧壁间隔物定位在半导体器件上的预定位置。 一层钴选择性地与下层反应以形成用作硬掩模的图像反转层。 然后通过蚀刻将亚微米特征转移到半导体材料的下层中。

公开(公告)号：US5661048A

公开(公告)日：1997-08-26

申请号：US408654

申请日：1995-03-21

申请人： Robert B. Davies ,  Chandrasekhara Sudhama ,  Frank K. Baker

发明人： Robert B. Davies ,  Chandrasekhara Sudhama ,  Frank K. Baker

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/4983 ,  H01L21/823857 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/4991 ,  H01L29/66659 ,  H01L29/7835

摘要： An insulated gate field effect transistor (10) having a reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor substrate (11) and a drain extension region (25) is formed in the dopant well (13). An oxide layer (26) is formed on the dopant well (13) wherein the oxide layer (26) has a thickness of at least 400 angstroms. A gate structure (61) having a gate shunt portion (32) over a thinned portion of the oxide (26) and a gate extension portion (58) over an unthinned portion of the oxide (26). The thinned portion of the oxide (26) forms a gate oxide of the field effect transistor (10) and the unthinned portion lowers a capacitance of the gate shunt portion (32) of the field effect transistor (10).

摘要翻译： 具有减小的栅极 - 漏极电容的绝缘栅场效应晶体管（10）和制造场效应晶体管（10）的方法。 掺杂剂阱（13）形成在半导体衬底（11）中，并且在掺杂剂阱（13）中形成漏极延伸区域（25）。 氧化物层（26）形成在掺杂剂阱（13）上，其中氧化物层（26）具有至少400埃的厚度。 栅极结构（61）具有在氧化物（26）的薄化部分上方的栅极分流部分（32）和位于氧化物（26）的未固化部分上的栅极延伸部分（58）。 氧化物（26）的减薄部分形成场效应晶体管（10）的栅极氧化物，并且未固化部分降低场效应晶体管（10）的栅极分流部分（32）的电容。

公开(公告)号：US5037777A

公开(公告)日：1991-08-06

申请号：US546801

申请日：1990-07-02

申请人： Thomas C. Mele ,  Wayne M. Paulson ,  Frank K. Baker ,  Michael P. Woo

发明人： Thomas C. Mele ,  Wayne M. Paulson ,  Frank K. Baker ,  Michael P. Woo

IPC分类号： H01L21/3105 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/3105 ,  Y10S148/133 ,  Y10S148/161 ,  Y10S438/978

摘要： The disclosed invention is a method for fabricating a multi-layer semiconductor device using selective planarization. In accordance with one embodiment of the invention, conductive members are formed on a substrate and a first insulating layer is deposited onto the substrate and the conductive members. A second insulating layer, which has a lower flow temperature than the flow temperature of the first layer, is deposited onto the first layer. A photoresist mask is patterned and developed to form a window which exposes an area between the conductive members. The device is preferentially etched such that only the exposed areas of the second insulating layer are removed, leaving the first insulating layer intact. An anisotropic etch is used to remove portions of the first insulating layer, leaving spacers along the edges of the conductive members. The photoresist mask is removed and a heating step is performed which flows the remaining portions of the second insulating layer, but not the first layer. Since the second insulating material remains in only selective areas, the process is termed selective planarization. The method provides the benefit that areas which are to be etched to form contact hole or vias are not planarized, unlike existing blanket planarization methods, and a self-aligned contact is formed between the conductive members to the substrate.

摘要翻译： 所公开的发明是使用选择性平坦化制造多层半导体器件的方法。 根据本发明的一个实施例，导电构件形成在衬底上，并且第一绝缘层沉积到衬底和导电构件上。 具有比第一层的流动温度低的流动温度的第二绝缘层沉积到第一层上。 对光致抗蚀剂掩模进行图案化和显影以形成露出导电构件之间的区域的窗口。 优先蚀刻器件，使得只有第二绝缘层的暴露区域被去除，留下第一绝缘层完好无损。 使用各向异性蚀刻去除第一绝缘层的部分，沿着导电构件的边缘留下间隔物。 去除光致抗蚀剂掩模，并且执行流过第二绝缘层的剩余部分而不是第一层的加热步骤。 由于第二绝缘材料仅保留在选择性区域中，所以该过程称为选择性平面化。 该方法提供了与现有的覆盖平面化方法不同的是要被蚀刻以形成接触孔或通孔的区域不平坦化的优点，并且在导电构件与基底之间形成自对准接触。

公开(公告)号：US5536674A

公开(公告)日：1996-07-16

申请号：US345891

申请日：1994-11-28

申请人： Yasunobu Kosa ,  Howard C. Kirsch ,  Thomas F. McNelly ,  Frank K. Baker

发明人： Yasunobu Kosa ,  Howard C. Kirsch ,  Thomas F. McNelly ,  Frank K. Baker

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11

摘要： A static-random-access memory cell comprising floating node capacitors is disclosed. In one embodiment, the storage nodes acts as the first plates for the floating node capacitors, and a conductive member acts as the second plates for the floating node capacitors. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cell. In another embodiment, a conductive member acts as the second plates of a plurality of memory cells. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cells. Processes for forming the memory cells is also disclosed.

摘要翻译： 公开了一种包括浮动节点电容器的静态随机存取存储器单元。 在一个实施例中，存储节点用作浮动节点电容器的第一板，并且导电构件用作浮动节点电容器的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 在另一个实施例中，导电构件用作多个存储单元的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 还公开了用于形成存储单元的工艺。

公开(公告)号：US5712501A

公开(公告)日：1998-01-27

申请号：US541536

申请日：1995-10-10

申请人： Robert B. Davies ,  Frank K. Baker ,  Jon J. Candelaria ,  Andreas A. Wild ,  Peter J. Zdebel

发明人： Robert B. Davies ,  Frank K. Baker ,  Jon J. Candelaria ,  Andreas A. Wild ,  Peter J. Zdebel

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/66583 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7838 ,  H01L29/66537

摘要： A graded-channel semiconductor device (10) includes a substrate region (11) having a major surface (12). A source region (13) and a drain region (14) are formed in the substrate region (11) and are spaced apart to form a channel region (16). A doped region (18) is formed in the channel region (16) and is spaced apart from the source region (13), the drain region (14), and the major surface (12). The doped region (18) has the same conductivity type as the channel region (16), but has a higher dopant concentration. The device (10) exhibits an enhanced punch-through resistance and improved performance compared to prior art short channel structures.

摘要翻译： 分级沟道半导体器件（10）包括具有主表面（12）的衬底区域（11）。 源区域（13）和漏极区域（14）形成在衬底区域（11）中并且间隔开以形成沟道区域（16）。 掺杂区域（18）形成在沟道区域（16）中并且与源极区域（13），漏极区域（14）和主表面（12）间隔开。 掺杂区域（18）具有与沟道区域（16）相同的导电类型，但具有较高的掺杂剂浓度。 与现有技术的短沟道结构相比，器件（10）表现出增强的穿通电阻和改进的性能。