公开(公告)号：US20050270197A1

公开(公告)日：2005-12-08

申请号：US10908741

申请日：2005-05-24

申请人： Sterling Smith ,  Chia-Ming Yang

发明人： Sterling Smith ,  Chia-Ming Yang

IPC分类号： G09G3/20 ,  H03M1/10 ,  H03M1/12 ,  H04N5/14

CPC分类号： H03M1/1028 ,  H03M1/12

摘要： A video signal processing system with a dynamic calibration loop of an ADC comprises a calibration switch for transmitting signals according to a control signal; a reference switch module for transmitting reference voltages according to a plurality of control signals; a reference voltage generator coupled to the reference switch module for providing the reference voltages; a coarse tuner coupled to the calibration switch and the reference switch module for coarse-tuning received signals; an ADC coupled to the coarse tuner for converting analog signals to digital signals; a fine-tuner coupled to the ADC for fine-tuning received signals; and a calibration logic module for controlling the calibration switch, the reference switch module, the coarse tuner, the ADC, and the fine tuner according to signals outputted from the fine tuner, so as to compensate errors of the ADC.

摘要翻译： 具有ADC的动态校准环路的视频信号处理系统包括用于根据控制信号发送信号的校准开关; 参考开关模块，用于根据多个控制信号传输参考电压; 耦合到参考开关模块的参考电压发生器，用于提供参考电压; 耦合到校准开关的粗调谐器和用于对接收信号进行粗调的参考开关模块; 耦合到粗调谐器的ADC，用于将模拟信号转换成数字信号; 耦合到ADC的微​​调器，用于微调接收信号; 以及校准逻辑模块，用于根据从精细调谐器输出的信号来控制校准开关，参考开关模块，粗调谐器，ADC和精细调谐器，以补偿ADC的误差。

公开(公告)号：US20050046491A1

公开(公告)日：2005-03-03

申请号：US10711175

申请日：2004-08-30

申请人： Sterling Smith

发明人： Sterling Smith

IPC分类号： H03L7/08 ,  H03L7/16 ,  H03L7/18 ,  H03L7/197 ,  H03L7/00

CPC分类号： H03L7/1976

摘要： A frequency synthesizer that includes two fractional dividers, two noise-shaped quantizers, three integer dividers, a PLL, an algorithm embodied in control logic, and an adjustment means. The noise-shaped quantizers are used to quantize two fractional (fixed-point) values, derived from the divider control words, into time-varying values. The dividers and PLL are used to generate an output signal by means of multiplying a reference signal by the quotient of the divider control word values. Accordingly, the frequency synthesizer of the present invention can provide a very precise output clock, with the average output frequency being the input frequency multiplied by the quotient of the two divider control words, and with high jitter stability.

摘要翻译： 一种频率合成器，包括两个分数分频器，两个噪声形量化器，三个整数除法器，PLL，控制逻辑中体现的算法，以及调整装置。 噪声量化器用于量化从分频器控制字导出的两个分数（定点）值到时变值。 分频器和PLL用于通过将参考信号乘以分频器控制字值的商来产生输出信号。 因此，本发明的频率合成器可以提供非常精确的输出时钟，平均输出频率是输入频率乘以两个分频器控制字的商，并具有高抖动稳定性。

公开(公告)号：US06714084B2

公开(公告)日：2004-03-30

申请号：US10144413

申请日：2002-05-09

申请人： Sterling Smith

发明人： Sterling Smith

IPC分类号： H03B2100

CPC分类号： H03L7/093 ,  H03K3/0322 ,  H03L7/0991

摘要： The present invention provides a frequency synthesis circuit. The frequency synthesis circuit includes a noise-shaping quantizer and a digitally controlled oscillator. The noise-shaping quantizer responsive to a plurality of input bits for shaping error signals resulting from the quantization conversion such that most of the error occurs at high frequency. The digitally controlled oscillator is connected to the output of the quantizer having an output frequency responsive to the output of the quantizer.

摘要翻译： 本发明提供一种频率合成电路。 频率合成电路包括噪声整形量化器和数字控制振荡器。 噪声整形量化器响应于多个输入比特，用于整形由量化转换产生的误差信号，使得大部分误差发生在高频。 数字控制振荡器连接到具有响应于量化器的输出的输出频率的量化器的输出端。

公开(公告)号：US07860913B2

公开(公告)日：2010-12-28

申请号：US11671430

申请日：2007-02-05

申请人： Hung-Kun Chen ,  Sterling Smith

发明人： Hung-Kun Chen ,  Sterling Smith

IPC分类号： G06F17/10

CPC分类号： H03H17/0664 ,  H03H17/0286 ,  H04N5/602

摘要： The invention discloses a finite impulse response (FIR) filter for processing a digital input signal to generate a digital output signal. The FIR filter has a tap amount N and a decimation ratio D. The FIR filter includes a first memory, a multiplier, and an accumulation module. For each input sample of the digital input signal, the first memory provides N/D corresponding tap coefficients from a plurality of tap coefficients in turn. The multiplier multiplies the input sample with the N/D corresponding tap coefficients in turn to generate N/D product values. The accumulation module adds the N/D product values to N/D previous accumulation values to generate N/D renewed accumulation values respectively. If one of the accumulation values has already accumulated N product values, the accumulation module outputs the accumulation value as an output sample of the digital output signal.

摘要翻译： 本发明公开了一种用于处理数字输入信号以产生数字输出信号的有限脉冲响应（FIR）滤波器。 FIR滤波器具有抽头量N和抽取比例D. FIR滤波器包括第一存储器，乘法器和累加模块。 对于数字输入信号的每个输入采样，第一存储器依次从多个抽头系数提供N / D对应的抽头系数。 乘数依次将输入采样与N / D对应的抽头系数相乘以产生N / D乘积值。 累加模块将N / D乘积值添加到N / D先前累积值，以分别产生N / D更新累积值。 如果积累值中的一个已经累积了N个乘积值，则累积模块输出累加值作为数字输出信号的输出样本。

公开(公告)号：US07564502B2

公开(公告)日：2009-07-21

申请号：US11163717

申请日：2005-10-28

申请人： Ke-Chiang Huang ,  Ta-Chan Kao ,  Sterling Smith

发明人： Ke-Chiang Huang ,  Ta-Chan Kao ,  Sterling Smith

IPC分类号： H04N5/52 ,  H03M1/12

CPC分类号： H03M1/1295 ,  H03L7/08 ,  H03M1/1255 ,  H03M1/183 ,  H04N5/52

摘要： An analog-to-digital converting system with automatic gain control. The analog-to-digital converting system includes a programmable gain amplifier (PGA) for receiving and amplifying an input signal by a gain factor to generate an amplified input signal; an ADC, coupled to the PGA, for converting the amplified input signal into a digital signal according to an actual reference voltage signal; and an automatic gain controller, coupled to the PGA and the ADC, for jointly controlling the gain factor set to the PGA and the actual reference voltage signal set to the ADC according to a hysteretic behavior.

摘要翻译： 具有自动增益控制的模数转换系统。 模数转换系统包括用于通过增益因子接收和放大输入信号以产生放大的输入信号的可编程增益放大器（PGA）; 耦合到PGA的ADC，用于根据实际的参考电压信号将放大的输入信号转换成数字信号; 以及耦合到PGA和ADC的自动增益控制器，用于根据迟滞行为共同控制设置到PGA的增益因子和设置到ADC的实际参考电压信号。

公开(公告)号：US20080123772A1

公开(公告)日：2008-05-29

申请号：US11671430

申请日：2007-02-05

申请人： Hung-Kun Chen ,  Sterling Smith

发明人： Hung-Kun Chen ,  Sterling Smith

IPC分类号： H04L25/49

CPC分类号： H03H17/0664 ,  H03H17/0286 ,  H04N5/602

摘要： The invention discloses a finite impulse response (FIR) filter for processing a digital input signal to generate a digital output signal. The FIR filter has a tap amount N and a decimation ratio D. The FIR filter includes a first memory, a multiplier, and an accumulation module. For each input sample of the digital input signal, the first memory provides N/D corresponding tap coefficients from a plurality of tap coefficients in turn. The multiplier multiplies the input sample with the N/D corresponding tap coefficients in turn to generate N/D product values. The accumulation module adds the N/D product values to N/D previous accumulation values to generate N/D renewed accumulation values respectively. If one of the accumulation values has already accumulated N product values, the accumulation module outputs the accumulation value as an output sample of the digital output signal.

摘要翻译： 本发明公开了一种用于处理数字输入信号以产生数字输出信号的有限脉冲响应（FIR）滤波器。 FIR滤波器具有抽头量N和抽取比例D. FIR滤波器包括第一存储器，乘法器和累加模块。 对于数字输入信号的每个输入采样，第一存储器依次从多个抽头系数提供N / D对应的抽头系数。 乘数依次将输入采样与N / D对应的抽头系数相乘以产生N / D乘积值。 累加模块将N / D乘积值添加到N / D先前累积值，以分别产生N / D更新累积值。 如果积累值中的一个已经累积了N个乘积值，则累积模块输出累加值作为数字输出信号的输出样本。

公开(公告)号：US07239355B2

公开(公告)日：2007-07-03

申请号：US10908473

申请日：2005-05-13

申请人： Sterling Smith ,  Jiunn-Kuang Chen ,  Hsu-Lin FanChiang

发明人： Sterling Smith ,  Jiunn-Kuang Chen ,  Hsu-Lin FanChiang

IPC分类号： H04N5/04

CPC分类号： G06T3/40 ,  H04N5/04

摘要： A video scaling apparatus includes a receiver for receiving incoming video signals having transmitted therein a plurality of incoming frames, each incoming frame having a first plurality of synchronization signals for indicating lines in the incoming frame; a scaler with a line extender for generating outgoing video signals having transmitted therein a plurality of outgoing frames, each outgoing frame having a second plurality of synchronization signals for indicating lines in the outgoing frame, and for generating an outgoing frame for each incoming frame. The line extender ensures durations of all lines in the outgoing video signals are of substantially equal length. By ensuring that all lines in the outgoing frame are of substantially the same length, the reliability of a display device receiving the outgoing video signals is increased. Additionally, the frequency requirements of an outgoing clock for the video signals can be less stringent.

摘要翻译： 视频缩放装置包括：接收器，用于接收在其中发送了多个输入帧的输入视频信号，每个输入帧具有用于指示输入帧中的行的第一多个同步信号; 具有线扩展器的缩放器，用于产生在其中发送了多个输出帧的输出视频信号，每个输出帧具有用于指示输出帧中的行的第二多个同步信号，并且用于为每个输入帧生成输出帧。 线延长器确保输出视频信号中的所有线的持续时间具有基本相等的长度。 通过确保输出帧中的所有线都具有基本相同的长度，接收输出视频信号的显示设备的可靠性增加。 此外，视频信号的输出时钟的频率要求可能不太严格。

公开(公告)号：US07231010B2

公开(公告)日：2007-06-12

申请号：US10619488

申请日：2003-07-16

申请人： Sterling Smith

发明人： Sterling Smith

IPC分类号： H03D3/24

CPC分类号： H03L7/0992 ,  H03L7/07

摘要： The present invention provides a phase-locked loop that comprises a divider, a noise-shaped quantizer, a filter, a phase detector and digital loop filter. The divider is used for receiving a reference clock with a substantially fixed period and generating an output clock with a time-varying period. The noise-shaped quantizer is used for quantizing a period control word to a time-varying value in response to the output clock fed from the divider so that the divider generates the output clock by means of dividing the reference clock by the time-varying value. The filter is employed to substantially filter out jitter from the output clock. The phase detector is used for generating a phase error in response to the filtered output clock and an input signal. The digital loop filter is used for generating the period control word in response to the phase error.

摘要翻译： 本发明提供了一种锁相环，其包括分频器，噪声形量化器，滤波器，相位检测器和数字环路滤波器。 分频器用于接收基本固定的周期的基准时钟，并产生具有时变周期的输出时钟。 噪声形量化器用于响应于从分频器馈送的输出时钟而将周期控制字量化为时变值，使得分频器通过将参考时钟除以时变值而产生输出时钟 。 滤波器用于基本上滤除输出时钟的抖动。 相位检测器用于响应于滤波的输出时钟和输入信号而产生相位误差。 数字环路滤波器用于响应于相位误差产生周期控制字。

公开(公告)号：US20060221242A1

公开(公告)日：2006-10-05

申请号：US11163127

申请日：2005-10-06

申请人： Ke-Chiang Huang ,  Ta-Chan Kao ,  Sterling Smith

发明人： Ke-Chiang Huang ,  Ta-Chan Kao ,  Sterling Smith

IPC分类号： H03L7/00 ,  H03M1/12

CPC分类号： H03M1/1295 ,  H03L7/08 ,  H03M1/1255 ,  H03M1/183 ,  H04N5/52

摘要： An analog-to-digital converting system for converting a composite video signal into a digital signal according to a synchronized clock. The analog-to-digital converting system includes an analog-to-digital converter (ADC), a color burst phase estimator and a phase-locked loop (PLL). The ADC converts the composite video signal to the digital signal according to the synchronized clock, wherein the synchronized clock is synchronized to a frequency of a color burst of a chrominance signal of the composite video signal. The color burst phase estimator, coupled to the ADC, estimates the phase of the color burst carried on the composite video signal. The PLL, coupled to the color burst phase estimator, generates the synchronized clock according to the phase of the color burst estimated by the color burst phase estimator.

摘要翻译： 一种用于根据同步时钟将复合视频信号转换为数字信号的模拟 - 数字转换系统。 模数转换系统包括模数转换器（ADC），色同步相位估计器和锁相环（PLL）。 ADC根据同步时钟将复合视频信号转换为数字信号，其中同步时钟与复合视频信号的色度信号的色同步信号的频率同步。 耦合到ADC的色同步相位估计器估计复合视频信号上携带的色同步信号的相位。 耦合到色同步相位估计器的PLL根据由色同步相位估计器估计的色同步脉冲的相位产生同步时钟。

公开(公告)号：US07106231B2

公开(公告)日：2006-09-12

申请号：US10904159

申请日：2004-10-27

申请人： Sterling Smith ,  Chia-Ming Yang ,  Chao-Ping Huang ,  Horng-Der Chang ,  Henry Tin-Hang Yung

发明人： Sterling Smith ,  Chia-Ming Yang ,  Chao-Ping Huang ,  Horng-Der Chang ,  Henry Tin-Hang Yung

IPC分类号： H03M1/10 ,  H03M1/12 ,  H04N5/18

CPC分类号： H03M1/1028 ,  H03M1/12

摘要： A video signal processing system capable of adjusting errors and related methods are introduced. The video signal processing system and related calibration methods utilize the characteristic of periodic breaks of video signals to perform various kinds of calibrations including gain calibration of ADC, offset calibration of ADC, dc-level shifting of input signals, and quatization errors spreading by adding analog random signals to input video signals. The required high accuracy in video signal processing systems is achieved in the present invention with the claimed calibration methods.

摘要翻译： 介绍了能够调整错误的视频信号处理系统和相关方法。 视频信号处理系统和相关校准方法利用视频信号周期性中断的特点，执行各种校准，包括ADC的增益校准，ADC的偏移校准，输入信号的直流电平移位，以及通过添加模拟 随机信号输入视频信号。 在所要求的校准方法的本发明中，在视频信号处理系统中所需的高精度是实现的。