公开(公告)号：US20050270197A1

公开(公告)日：2005-12-08

申请号：US10908741

申请日：2005-05-24

申请人： Sterling Smith ,  Chia-Ming Yang

发明人： Sterling Smith ,  Chia-Ming Yang

IPC分类号： G09G3/20 ,  H03M1/10 ,  H03M1/12 ,  H04N5/14

CPC分类号： H03M1/1028 ,  H03M1/12

摘要： A video signal processing system with a dynamic calibration loop of an ADC comprises a calibration switch for transmitting signals according to a control signal; a reference switch module for transmitting reference voltages according to a plurality of control signals; a reference voltage generator coupled to the reference switch module for providing the reference voltages; a coarse tuner coupled to the calibration switch and the reference switch module for coarse-tuning received signals; an ADC coupled to the coarse tuner for converting analog signals to digital signals; a fine-tuner coupled to the ADC for fine-tuning received signals; and a calibration logic module for controlling the calibration switch, the reference switch module, the coarse tuner, the ADC, and the fine tuner according to signals outputted from the fine tuner, so as to compensate errors of the ADC.

摘要翻译： 具有ADC的动态校准环路的视频信号处理系统包括用于根据控制信号发送信号的校准开关; 参考开关模块，用于根据多个控制信号传输参考电压; 耦合到参考开关模块的参考电压发生器，用于提供参考电压; 耦合到校准开关的粗调谐器和用于对接收信号进行粗调的参考开关模块; 耦合到粗调谐器的ADC，用于将模拟信号转换成数字信号; 耦合到ADC的微​​调器，用于微调接收信号; 以及校准逻辑模块，用于根据从精细调谐器输出的信号来控制校准开关，参考开关模块，粗调谐器，ADC和精细调谐器，以补偿ADC的误差。

公开(公告)号：US20050270212A1

公开(公告)日：2005-12-08

申请号：US10908743

申请日：2005-05-24

申请人： Sterling Smith ,  Chia-Ming Yang ,  Chih-Shiun Lu

发明人： Sterling Smith ,  Chia-Ming Yang ,  Chih-Shiun Lu

IPC分类号： H03M1/10 ,  H03M1/12

CPC分类号： H03M1/1028 ,  H03M1/1215

摘要： A high-speed video signal processing system, which includes a reception end for receiving analog signals; a plurality of analog to digital converters coupled to the reception end for converting analog signals received from the reception end to digital signals according to control signals; and an interleaving controller coupled to the plurality of analog to digital converters for generating the control signals to selectively enable the plurality of analog to digital converters according to a predetermined sequence.

摘要翻译： 一种高速视频信号处理系统，包括用于接收模拟信号的接收端; 耦合到接收端的多个模数转换器，用于根据控制信号将从接收端接收的模拟信号转换成数字信号; 以及耦合到所述多个模数转换器的交织控制器，用于产生所述控制信号，以根据预定顺序选择性地启用所述多个模数转换器。

公开(公告)号：US07106231B2

公开(公告)日：2006-09-12

申请号：US10904159

申请日：2004-10-27

申请人： Sterling Smith ,  Chia-Ming Yang ,  Chao-Ping Huang ,  Horng-Der Chang ,  Henry Tin-Hang Yung

发明人： Sterling Smith ,  Chia-Ming Yang ,  Chao-Ping Huang ,  Horng-Der Chang ,  Henry Tin-Hang Yung

IPC分类号： H03M1/10 ,  H03M1/12 ,  H04N5/18

CPC分类号： H03M1/1028 ,  H03M1/12

摘要： A video signal processing system capable of adjusting errors and related methods are introduced. The video signal processing system and related calibration methods utilize the characteristic of periodic breaks of video signals to perform various kinds of calibrations including gain calibration of ADC, offset calibration of ADC, dc-level shifting of input signals, and quatization errors spreading by adding analog random signals to input video signals. The required high accuracy in video signal processing systems is achieved in the present invention with the claimed calibration methods.

摘要翻译： 介绍了能够调整错误的视频信号处理系统和相关方法。 视频信号处理系统和相关校准方法利用视频信号周期性中断的特点，执行各种校准，包括ADC的增益校准，ADC的偏移校准，输入信号的直流电平移位，以及通过添加模拟 随机信号输入视频信号。 在所要求的校准方法的本发明中，在视频信号处理系统中所需的高精度是实现的。

公开(公告)号：US07084795B2

公开(公告)日：2006-08-01

申请号：US10908741

申请日：2005-05-24

申请人： Sterling Smith ,  Chia-Ming Yang

发明人： Sterling Smith ,  Chia-Ming Yang

IPC分类号： H03M1/10

CPC分类号： H03M1/1028 ,  H03M1/12

摘要： A video signal processing system with a dynamic calibration loop of an ADC comprises a calibration switch for transmitting signals according to a control signal; a reference switch module for transmitting reference voltages according to a plurality of control signals; a reference voltage generator coupled to the reference switch module for providing the reference voltages; a coarse tuner coupled to the calibration switch and the reference switch module for coarse-tuning received signals; an ADC coupled to the coarse tuner for converting analog signals to digital signals; a fine-tuner coupled to the ADC for fine-tuning received signals; and a calibration logic module for controlling the calibration switch, the reference switch module, the coarse tuner, the ADC, and the fine tuner according to signals outputted from the fine tuner, so as to compensate errors of the ADC.

摘要翻译： 具有ADC的动态校准环路的视频信号处理系统包括用于根据控制信号发送信号的校准开关; 参考开关模块，用于根据多个控制信号传输参考电压; 耦合到参考开关模块的参考电压发生器，用于提供参考电压; 耦合到校准开关的粗调谐器和用于对接收信号进行粗调的参考开关模块; 耦合到粗调谐器的ADC，用于将模拟信号转换成数字信号; 耦合到ADC的微​​调器，用于微调接收信号; 以及校准逻辑模块，用于根据从精细调谐器输出的信号来控制校准开关，参考开关模块，粗调谐器，ADC和精细调谐器，以补偿ADC的误差。

公开(公告)号：US20050093722A1

公开(公告)日：2005-05-05

申请号：US10904159

申请日：2004-10-27

申请人： Sterling Smith ,  Chia-Ming Yang ,  Chao-Ping Huang ,  Horng-Der Chang ,  Henry Yung

发明人： Sterling Smith ,  Chia-Ming Yang ,  Chao-Ping Huang ,  Horng-Der Chang ,  Henry Yung

IPC分类号： H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/34 ,  H04N5/14

CPC分类号： H03M1/1028 ,  H03M1/12

摘要： A video signal processing system capable of adjusting errors and related methods are introduced. The video signal processing system and related calibration methods utilize the characteristic of periodic breaks of video signals to perform various kinds of calibrations including gain calibration of ADC, offset calibration of ADC, dc-level shifting of input signals, and quatization errors spreading by adding analog random signals to input video signals. The required high accuracy in video signal processing systems is achieved in the present invention with the claimed calibration methods.

摘要翻译： 介绍了能够调整错误的视频信号处理系统和相关方法。 视频信号处理系统和相关校准方法利用视频信号周期性中断的特点，执行各种校准，包括ADC的增益校准，ADC的偏移校准，输入信号的直流电平移位，以及通过添加模拟 随机信号输入视频信号。 在所要求的校准方法的本发明中，在视频信号处理系统中所需的高精度是实现的。

公开(公告)号：US07471339B2

公开(公告)日：2008-12-30

申请号：US10908743

申请日：2005-05-24

申请人： Sterling Smith ,  Chia-Ming Yang ,  Chih-Shiun Lu

发明人： Sterling Smith ,  Chia-Ming Yang ,  Chih-Shiun Lu

IPC分类号： H03M1/12

CPC分类号： H03M1/1028 ,  H03M1/1215

摘要： A high-speed video signal processing system, which includes a reception end for receiving analog signals; a plurality of analog to digital converters coupled to the reception end for converting analog signals received from the reception end to digital signals according to control signals; and an interleaving controller coupled to the plurality of analog to digital converters for generating the control signals to selectively enable the plurality of analog to digital converters according to a predetermined sequence.

摘要翻译： 一种高速视频信号处理系统，包括用于接收模拟信号的接收端; 耦合到接收端的多个模数转换器，用于根据控制信号将从接收端接收的模拟信号转换成数字信号; 以及耦合到所述多个模数转换器的交织控制器，用于产生所述控制信号，以根据预定顺序选择性地启用所述多个模数转换器。

公开(公告)号：US20110032978A1

公开(公告)日：2011-02-10

申请号：US12769905

申请日：2010-04-29

申请人： PO-NIEN LIN ,  Sterling Smith

发明人： PO-NIEN LIN ,  Sterling Smith

IPC分类号： H04L27/01

CPC分类号： H04L25/03076

摘要： A receiver includes an adaptive equalizer, a power detecting unit and an adjusting unit. The adaptive equalizer is for receiving a signal and generating an equalized signal. The power detecting unit, coupled to the adaptive equalizer, is for detecting the strength of the equalized signal during a first period to generate a first strength signal, and detecting the strength of the equalized signal during a second period to generate a second strength signal. The adjusting unit, coupled to the power detecting unit and the adaptive equalizer, is for adjusting the compensation strength for the adaptive equalizer according to the first and second strength signals.

摘要翻译： 接收机包括自适应均衡器，功率检测单元和调整单元。 自适应均衡器用于接收信号并产生均衡的信号。 耦合到自适应均衡器的功率检测单元用于在第一周期期间检测均衡信号的强度以产生第一强度信号，并且在第二周期期间检测均衡信号的强度以产生第二强度信号。 耦合到功率检测单元和自适应均衡器的调整单元用于根据第一和第二强度信号调整自适应均衡器的补偿强度。

公开(公告)号：US07795937B2

公开(公告)日：2010-09-14

申请号：US12402815

申请日：2009-03-12

申请人： Sterling Smith ,  Ellen Chen Yeh ,  Wen cai Lu

发明人： Sterling Smith ,  Ellen Chen Yeh ,  Wen cai Lu

IPC分类号： H03L7/06

CPC分类号： H04N5/126 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0996

摘要： A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.

摘要翻译： 具有自动调整锁定精度的校准机制的可扩展DLL（延迟锁定环路）电路。 延迟锁定环电路包括用于根据系统时钟产生多个相位信号的多相锁相环电路，其中相位信号之一是像素时钟; 相位检测器，用于根据像素时钟检测参考信号和反馈信号之间的积分相位误差和分数相位误差; 相位选择器，用于根据分数相位误差选择一个相位信号; 以及延迟电路，用于根据积分相位误差和所选择的相位信号偏移参考信号的相位，以产生输出信号。

公开(公告)号：US20080144358A1

公开(公告)日：2008-06-19

申请号：US11889695

申请日：2007-08-15

申请人： Sterling Smith ,  Chung-Ho Ning

发明人： Sterling Smith ,  Chung-Ho Ning

IPC分类号： G11C11/24

CPC分类号： G06K19/0723 ,  G06K19/0701

摘要： A read state retention circuit and method are disclosed. The read state retention circuit comprises a charge storage unit, charging unit, sensing circuit and state indicator. The charging circuit is coupled to the charge storage unit for charging the charge storage unit. The sensing circuit is coupled to the charge storage unit for sensing a voltage level of the charge storage unit. The state indicator is coupled to the sensing circuit for outputting an indication signal in response to the voltage level.

摘要翻译： 公开了一种读取状态保持电路和方法。 读取状态保持电路包括电荷存储单元，充电单元，感测电路和状态指示器。 充电电路耦合到电荷存储单元以对电荷存储单元进行充电。 感测电路耦合到电荷存储单元，用于感测电荷存储单元的电压电平。 状态指示器耦合到感测电路，用于响应于电压电平输出指示信号。

公开(公告)号：US07315602B2

公开(公告)日：2008-01-01

申请号：US10615845

申请日：2003-07-10

申请人： Sterling Smith

发明人： Sterling Smith

IPC分类号： H03D3/24 ,  H04B14/06 ,  H03L25/00 ,  H03B21/00

CPC分类号： H03L7/16 ,  H04B1/707

摘要： The present invention provides a digital spread spectrum frequency synthesizer that comprises a noise-shaped quantizer, a divider and an adjustment means. The noise-shaped quantizer is used to quantize a period control word to a time-varying value. The divider is used for generating an output signal by means of dividing a reference signal by the time-varying value, the output signal feeding back to the noise-shaped quantizer so that the noise-shaped quantizer generates the time-varying value in response to the feedback output signal. The adjustment means is used to adjust the period control word by a period offset in response to the output clock. Accordingly, the frequency synthesizer of the present invention can provide a very precise frequency synthesizer featuring a precision spread spectrum clock and jitter stability as well.

摘要翻译： 本发明提供了一种数字扩频频率合成器，其包括噪声形量化器，分频器和调整装置。 噪声形量化器用于将周期控制字量化到时变值。 分频器用于通过将参考信号除以时变值来产生输出信号，该输出信号反馈到噪声形量化器，使得噪声形量化器响应于 反馈输出信号。 调整装置用于响应于输出时钟调整周期控制字周期偏移。 因此，本发明的频率合成器可以提供具有精确扩频时钟和抖动稳定性的非常精确的频率合成器。