摘要:
A video signal processing system capable of adjusting errors and related methods are introduced. The video signal processing system and related calibration methods utilize the characteristic of periodic breaks of video signals to perform various kinds of calibrations including gain calibration of ADC, offset calibration of ADC, dc-level shifting of input signals, and quatization errors spreading by adding analog random signals to input video signals. The required high accuracy in video signal processing systems is achieved in the present invention with the claimed calibration methods.
摘要:
A video signal processing system capable of adjusting errors and related methods are introduced. The video signal processing system and related calibration methods utilize the characteristic of periodic breaks of video signals to perform various kinds of calibrations including gain calibration of ADC, offset calibration of ADC, dc-level shifting of input signals, and quatization errors spreading by adding analog random signals to input video signals. The required high accuracy in video signal processing systems is achieved in the present invention with the claimed calibration methods.
摘要:
A video signal processing system with a dynamic calibration loop of an ADC comprises a calibration switch for transmitting signals according to a control signal; a reference switch module for transmitting reference voltages according to a plurality of control signals; a reference voltage generator coupled to the reference switch module for providing the reference voltages; a coarse tuner coupled to the calibration switch and the reference switch module for coarse-tuning received signals; an ADC coupled to the coarse tuner for converting analog signals to digital signals; a fine-tuner coupled to the ADC for fine-tuning received signals; and a calibration logic module for controlling the calibration switch, the reference switch module, the coarse tuner, the ADC, and the fine tuner according to signals outputted from the fine tuner, so as to compensate errors of the ADC.
摘要:
A video signal processing system with a dynamic calibration loop of an ADC comprises a calibration switch for transmitting signals according to a control signal; a reference switch module for transmitting reference voltages according to a plurality of control signals; a reference voltage generator coupled to the reference switch module for providing the reference voltages; a coarse tuner coupled to the calibration switch and the reference switch module for coarse-tuning received signals; an ADC coupled to the coarse tuner for converting analog signals to digital signals; a fine-tuner coupled to the ADC for fine-tuning received signals; and a calibration logic module for controlling the calibration switch, the reference switch module, the coarse tuner, the ADC, and the fine tuner according to signals outputted from the fine tuner, so as to compensate errors of the ADC.
摘要:
A high-speed video signal processing system, which includes a reception end for receiving analog signals; a plurality of analog to digital converters coupled to the reception end for converting analog signals received from the reception end to digital signals according to control signals; and an interleaving controller coupled to the plurality of analog to digital converters for generating the control signals to selectively enable the plurality of analog to digital converters according to a predetermined sequence.
摘要:
A high-speed video signal processing system, which includes a reception end for receiving analog signals; a plurality of analog to digital converters coupled to the reception end for converting analog signals received from the reception end to digital signals according to control signals; and an interleaving controller coupled to the plurality of analog to digital converters for generating the control signals to selectively enable the plurality of analog to digital converters according to a predetermined sequence.
摘要:
The invention discloses a sensitive field effect transistor apparatus, which uses an inorganic membrane to sense hydrogen ions. The invention adopts the membrane with high deformation stress. The sensitivity of the sensitive membrane to hydrogen ions is adjusted through altering the membrane thickness and changing the substrate type and doped concentration. A differential amplifier is used to read a signal to form the inorganic Ion Sensitive Field Effect Transistor/Reference Field Effect Transistor apparatus.
摘要:
A biosensor applicable to an environment suitable for biosensing is provided, which is a solid-state element for performing detections in an aqueous environment. The biosensor at least includes a biosensing layer, a light-emitting diode and a photodiode. The biosensing layer causes changes in the light-emitting property thereof after absorbing, adsorbing and/or bonding with a biological substance released during in vivo signal transduction in an organism, and the rays of light generated by excitation of the light-emitting diode causes the biosensing layer to emit fluorescence. After the fluorescence is absorbed by the photodiode, it can be converted into an interpretable photocurrent signal. Afterwards, the meaning of the in vivo signal transduction can be understood by interpretation of the photocurrent signal.
摘要:
A method of forming a metal feature in a low-k dielectric layer is provided. The method includes forming an opening in a low-k dielectric layer, forming a metal layer having a substantially planar surface over the low-k dielectric layer using spin-on method, and stress free polishing the metal layer. Preferably, the metal layer comprises copper or copper alloys. The metal layer preferably includes a first sub layer having a substantially non-planar surface and a second sub layer having a substantially planar surface on the first sub layer.
摘要:
A multicarrier direct-sequence code-division multiple-access (MC-DS/CDMA) communications system is provided. A code tree of two-dimensional orthogonal variable spreading factor (2D-OVSF) codes is then generated for the system. To generate the code tree, a set of existing M1×N1 2D-OVSF matrices, in the form of A(i)(M1×N1) for i={1, 2, . . . , K1} is selected as seed matrices. M1 represents the number of available frequency carriers in the MC-DS/CDMA system, and N1 represents a spreading factor code length. Another set of existing M2×N2 2D-OVSF matrices, in the form of B2(i)(M2×N2) for i={1, 2, . . . , K2} is then selected as mapping matrices. The mapping matrices are used to generate corresponding children matrices. These second layer child matrices are M1M2×N1N2 matrices with cardinality K1K2, which are defined by reiterating the relationship: C ( M 1 M 2 × N 1 N 2 ) ( ( i - 1 ) K 2 + 1 ) = B 2 ( M 2 × N 2 ) ( 1 ) ⊕ A ( M 1 × N 1 ) ( i ) C ( M 1 M 2 × N 1 N 2 ) ( ( i - 1 ) K 2 + 2 ) = B 2 ( M 2 × N 2 ) ( 2 ) ⊕ A ( M 1 × N 1 ) ( i ) ⋯ C ( M 1 M 2 × N 1 N 2 ) ( ( i - 1 ) K 2 + K 2 ) = B 2 ( M 2 × N 2 ) ( K 2 ) ⊕ A ( M 1 × N 1 ) ( i ) where ⊕ indicates a Kronecker product, and i=1, 2, 3, 4, . . . , K1.